Devices, and the amplitude they stop being linear at

The frequency a device sets for itself

A common-emitter stage's bandwidth is decided by two picofarads between its collector and its base. The Miller approximation says how — lump it at the input, multiplied by one plus the gain — and predicts 643 kHz where the solved network gives 503 kHz. Twenty-two per cent optimistic, and it has no room at all for the second pole or for the zero in the right half-plane that the network also has.

A transistor has capacitance inside it, and one of the capacitances is in a much worse place than the other.

The capacitance across the base-emitter junction sits at the input, in parallel with everything else at the input, and does what a capacitance at an input does. The capacitance between base and collector sits across the stage, and the stage has a large inverting gain. Two picofarads connected between two nodes that move in opposite directions by a factor of a hundred and forty-five draws a current a hundred and forty-six times larger than its own admittance suggests, and the source has to supply all of it.

A common-emitter stage with 2.0 pF from collector to basecomputed by solving, not by drawing. The stage's midband gain is 144.7 and its −3 dB point is at 503 kHz. The Miller approximation lumps 311 pF at the input and predicts 643 kHz — 21.7% high. The network's second pole is at 336 MHz and its right-half-plane zero at 3.08 GHz, both of which the approximation has no room for.-20020401001k10k100k1M10M100M1G10Gfrequency (hertz)gain (decibels)midband 43.2 dBsolved: 503 kHzMiller says 643 kHzsecond pole 336 MHzzero at g_m/C_μsolved, then checked — two networks, one measurementMiller is 22% optimistic
Fig. 1 A common-emitter stage with two picofarads from collector to base, drawn twice: as the network, and as the Miller approximation to it. Both are netlists, and both bandwidths are measured the same way — by bisecting the solved magnitude for its −3 dB point — so the comparison is between two circuits rather than between a circuit and a formula. The slider is the collector-base capacitance.

What the approximation says, and what it leaves out

The Miller argument is one of the genuinely useful approximations in the subject, and it is short. The current through a capacitance between two nodes depends on the voltage across it. If one node carries v and the other carries −Av, the voltage across it is (1 + A)v, so the current it draws from the first node is (1 + A) times what it would draw if the far end were grounded. As far as the input is concerned, a capacitance C_μ between input and output is a capacitance C_μ(1 + A) to ground.

For the stage drawn here that turns 2 pF into 291 pF, which with the 20 pF already across the input gives 311 pF where a naive count would have said 22 pF. That is a factor of fourteen in the input capacitance and the single most consequential number in the stage.

What the argument then does — and this is where it stops being exact — is treat the resulting circuit as having one pole. It does not. The original network has capacitance at two nodes and a forward path through the capacitance, so it has two poles and a zero; the approximation has one node with capacitance and therefore one pole and nothing else.

Both as networks, measured the same way

The comparison here is deliberately not between a circuit and an expression. Both the stage and its Miller approximation are built as netlists — the approximation is a real circuit with a 311 pF capacitor in it — and both are solved and bisected for their −3 dB points by the same routine.

The measured −3 dB point of the network is 503.13 kHz. The measured −3 dB point of the approximation is 642.84 kHz. The approximation is 21.7% optimistic.

That figure holds its character across the slider. At half a picofarad it is 18.9% optimistic, at two picofarads 21.7%, at eight 22.6% — growing slowly and never small. A designer who uses the Miller estimate and finds the measured bandwidth twenty per cent lower has not made a mistake; they have used a model whose error is twenty per cent.

A common-emitter stage with 8.0 pF from collector to basecomputed by solving, not by drawing. The stage's midband gain is 144.7 and its −3 dB point is at 131 kHz. The Miller approximation lumps 1186 pF at the input and predicts 169 kHz — 22.6% high. The network's second pole is at 324 MHz and its right-half-plane zero at 770 MHz, both of which the approximation has no room for.-20020401001k10k100k1M10M100M1G10Gfrequency (hertz)gain (decibels)midband 43.2 dBsolved: 131 kHzMiller says 169 kHzsecond pole 324 MHzzero at g_m/C_μsolved, then checked — two networks, one measurementMiller is 23% optimistic
Fig. 2 The same stage with four times the collector-base capacitance. The input capacitance is 1,186 pF, the bandwidth has fallen to 131 kHz, and the approximation is now 22.6% optimistic. The right-half-plane zero has come down by the same factor of four, to 770 MHz — it is g_m/C_μ exactly, so it moves with the capacitance in the opposite direction to the pole.

The zero the approximation cannot have

The network has a zero in the right half of the complex plane, at 3.078 GHz for the two-picofarad case, and it is at exactly g_m/2πC_μ.

That equality is asserted rather than observed: the transconductance is 38.68 mS and the capacitance 2 pF, giving 3.0782 GHz, and the zero recovered from the network’s polynomial agrees to better than a part in 10⁹. It is worth knowing where it comes from, because a right-half-plane zero is a strange object and this one has a very concrete cause.

At any frequency the output current has two contributions: the transistor’s, g_mv, flowing from collector to emitter, and the capacitance’s, sCv, flowing forward from base to collector. They oppose. At low frequency the transistor wins by a wide margin. At s = g_m/C_μ they are equal and the output is zero. Above it the capacitance wins, and the signal that reaches the collector has gone straight through the capacitor rather than through the transistor — with the opposite sign, which is what “right half-plane” means for the phase.

A signal path through the component that was supposed to be a parasitic is a very literal description of what a right-half-plane zero is, and it explains why the Miller approximation cannot represent it: the approximation removed the component from between the two nodes and put it at one of them, which is exactly the step that deletes the forward path.

Two poles, and the trouble with finding the second

The network’s poles come out at 503.9 kHz and 335.9 MHz — three and a half decades apart.

Recovering both took a change of units, and the reason is worth recording because it looks like a numerical detail and is a real trap. This site’s transferFunction lifts the characteristic polynomial out of the matrix by sampling and then discards leading coefficients that are small relative to the largest, which is right: that is what distinguishes a genuine degree from arithmetic dust. With two poles three and a half decades apart, the s² coefficient is 10⁻¹⁷ of the constant term, and in raw units that is not distinguishable from dust. The trim removed it, the recovery returned a first-order polynomial, and the stage appeared to have one pole — which is precisely the claim this page exists to contradict.

The fix is to measure time in units of 1/ω₀ before asking. Multiplying every capacitance and inductance by ω₀ leaves the same circuit with its frequency axis rescaled; the poles come back as numbers near one, the coefficients land within a few decades of each other, and multiplying the roots by ω₀ afterwards undoes it. Nothing about the circuit changes and the trim then has something to work with.

Two poles at ζ = 0.3, recovered from the matrixThe poles are at -477.4 ± j1518 hertz. Their distance from the origin is the natural frequency to six digits; the cosine of their angle from the negative real axis is the damping ratio. The step response beside them follows.the step this produces00.50011.5001234σζ = 0.3000ω₀ = 1592 Hzsolved, then checked — poles by rooting the determinantnatural frequency recovered to 6 digits
Fig. 3 Poles in the complex plane, from the transients field. A pole is where the network’s matrix loses rank, and the two poles of this stage sit on the negative real axis at 503.9 kHz and 335.9 MHz. The dominant one is the bandwidth; the other is far enough away to be irrelevant to the magnitude and close enough to matter to the phase, which is where it does its damage.

Why the second pole matters anyway

Three and a half decades is a long way, and it is tempting to conclude that the second pole can be ignored. For the magnitude, it very nearly can: the measured −3 dB point of 503.13 kHz differs from the dominant pole’s 503.89 kHz by 0.15%, which is the combined effect of the second pole and the zero and is not worth arguing about.

For the phase it cannot. A pole contributes −45° at its own frequency and −5.7° a decade below it, and the feedback field is entirely about what an extra few degrees of lag at the crossover frequency does to a margin. Two measurements of one margin shows a phase margin from the loop gain and one from the measured overshoot agreeing to 0.1°, and what makes that a strong result is that a tenth of a degree is a quantity the circuit actually notices.

A stage whose second pole is at 336 MHz is contributing about 0.09° of lag at 503 kHz, which is nothing. Put three such stages in a loop that crosses over at 30 MHz and each contributes 5°, and the design has spent fifteen degrees of margin on poles that a single-pole model does not contain.

A gain of 100 asked of an amplifier with 1.00 MHz of gain–bandwidthThe ideal amplifier — a nullor, so the two golden rules exactly — holds 100 at every frequency. The real one is 0.10% low at direct current, 1% low by 1.35 kHz, and 3 dB down at 10.0 kHz. Above 10.0 kHz there is no loop gain left and the ideal answer is not an approximation to anything.010203040501101001k10k100k1Mfrequency (hertz)closed-loop gain (decibels)the ideal amplifier: two resistors, no frequencythe circuit+1% low at 1.35 kHz3 dB down at 10.0 kHzsolved, then checked — a nullor against a real devicethe ideal answer is 1% wrong above 1.35 kHz
Fig. 4 An amplifier with a flat gain and the same amplifier with the bandwidth its parts give it, from the feedback field. The stage on this page is one contribution to a curve like that one, and the argument is the same at both scales: the flat model is excellent inside a range, the range is a number, and the number is smaller than most readers expect.

Where the twenty-two per cent comes from

The approximation’s error is unusually stable across the slider — 18.9%, 21.7%, 22.6% for half, two and eight picofarads — and stability of that kind usually means a single mechanism rather than several.

It is one mechanism, and it is the load side. The Miller argument accounts for what C_μ does at the input and silently assumes it does nothing at the output. It does something: the same capacitance is also across the output node, contributing C_μ(1 + 1/A) there, which for a gain of 145 is very nearly C_μ itself. Two picofarads across a load of a few kilohms is a second pole in the hundreds of megahertz — the one recovered above at 336 MHz — and it is far enough away to move the −3 dB point by only a fraction of a per cent.

So the output side is not the explanation. The explanation is at the input, and it is that the gain used in the multiplication is not constant. The Miller factor (1 + A) uses the midband gain, and at the −3 dB point the stage’s gain has already fallen by a factor of √2 — so the actual multiplication near the corner is smaller than the one the approximation used, which should make the approximation pessimistic rather than optimistic.

The sign works out the other way because the approximation compares the wrong pair of circuits. Its single pole sits at 1/2πR_sC_in with R_s the source resistance in parallel with r_π, a combination the real network also has — and the real network’s dominant pole additionally sees the zero pulling the response down and the second pole starting to contribute. The measured pole of the network, 503.9 kHz, is below the approximation’s 642.8 kHz by very nearly the ratio of the two input capacitances as the frequency approaches the corner.

The useful conclusion is not the mechanism but its stability: an error that sits between eighteen and twenty-three per cent over a sixteen-fold variation in the parameter is a correctable one. The measured ratio of solved bandwidth to predicted is 0.811, 0.783 and 0.774 at half, two and eight picofarads, so multiplying the Miller estimate by about 0.78 lands within four per cent everywhere on the slider. That is what an experienced designer’s rule of thumb amounts to, and it is the kind of correction that never gets written down because the approximation it corrects is usually quoted without an error in the first place.

What the schematic is not telling anyone

There is a drawing convention buried in all of this that is worth surfacing, because it is the reason the Miller effect surprises people who have looked at the schematic a hundred times.

C_μ is not on the schematic. It is inside the transistor symbol, along with C_π, and the symbol shows neither. A stage drawn with a source, a resistor, a transistor and a load looks like a circuit with no capacitors in it at all, and its bandwidth looks like something that ought to be infinite. The two picofarads that decide the answer are in the datasheet, three pages in, under a heading that does not mention bandwidth.

This site’s habit is that a schematic is a label rather than a drawing — the layout carries no information, so it is put small and in a corner and the canvas is given to the response. The corollary is on this page: a schematic that omits the components that decide the answer is not a compressed version of the circuit, it is a different circuit. The figures here show the netlist that was actually solved, which has every capacitance in it explicitly, and that is the only version in which the answer is derivable from the picture.

Impedance of a series RLC of Q = 4, measured by driving itOne ampere is forced into the terminals at each frequency and the resulting voltage is the impedance. The minimum is 7.91 Ω at 5.03 kHz.1101001k10k1001k10k100k1Mfrequency (hertz)impedance magnitude (ohms)reactances cancel at 5.03 kHz7.91 Ωsolved, then checked — one ampere in, 201 frequenciesnot a component value: what the pair does
Fig. 5 The impedance looking into a node, swept. The Miller multiplication is exactly a statement about this quantity at the input of the stage: the input admittance is not the capacitance drawn between the terminals but that capacitance multiplied by one plus the gain, and a measurement of the input impedance is the most direct way to see it. Nothing in the transistor symbol suggests any of it.

The transit frequency, and what a stage actually gets

The device’s own figure of merit is the transit frequency: the frequency at which its current gain falls to one, g_m/2π(C_π + C_μ). For the parameters here that is 279.8 MHz.

The stage delivers a gain of 144.7 and a bandwidth of 503 kHz, whose product is 72.8 MHz. So the circuit gets about a quarter of the device’s transit frequency as a gain-bandwidth product, and where the rest went is the substance of the stage’s design: the source resistance drives the input capacitance, and that combination decides the pole rather than anything internal to the device.

The consequence is that a stage’s bandwidth is not a device property at all. Change the source resistance and it moves; change the load and both the gain and the Miller multiplication move with it. The transit frequency is an upper bound the arrangement cannot exceed, and the arrangement usually falls a long way short.

A single-pole low-pass with its corner at 995 HzSolved at 209 frequencies. The straight-line sketch, drawn faintly, is 3.01 dB wrong at the corner and within a tenth of a decibel only below 152 Hz. The phase is already −5.7° a decade before the corner and −84° a decade after it.-60-40-200gain (decibels)the sketch: flat, then −20 dB/decade−3.01 dB-90-450101001k10k100kfrequency (hertz)phase (degrees)sketch within 0.1 dB below 152 Hzsolved, then checked — checked against a chain-matrix productthe sketch is 3.01 dB wrong at 995 Hz
Fig. 6 A single-pole response, and the straight-line sketch every engineer draws over it. The sketch is 3.01 dB wrong at the corner. The stage on this page has a response that looks exactly like this one over four decades — one pole, twenty decibels a decade — and it has two poles and a zero, none of which is visible until the axis is extended to ten gigahertz.

What is being claimed

The stage has a bandwidth of 503 kHz, and that number came out of a solved network rather than an expression.

The Miller approximation predicts 643 kHz. It is a good approximation in the sense that matters most — it identifies the right mechanism, gives the right dependence on gain and capacitance, and is wrong by a fixed twenty per cent rather than by an amount that varies wildly — and it is a bad one in the sense the site cares about, which is that it is normally quoted with no error attached.

The two things it cannot represent at all are the second pole and the right-half-plane zero, and both are consequences of the same step: moving a component from between two nodes to one of them deletes the path through it. That step is what makes the approximation tractable and it is what makes it incomplete, and the two facts are the same fact.

The site’s rule asks every figure to carry the frequency at which the model in it stops being true, and this page has three answers rather than one, which is unusual and worth ending on. The bandwidth — 503 kHz — is where the stage’s own flat-gain model gives out. The second pole — 336 MHz — is where its single-pole model gives out, and that is three and a half decades higher and matters only to phase. The zero — 3.08 GHz — is where the transistor stops being the thing that carries the signal, and above it the circuit is a capacitive divider with a transistor attached.

Three boundaries, three orders of magnitude apart, all belonging to the same two picofarads. Which one is “the” limit depends entirely on what is being asked, and a single number quoted without that context is the thing this collection exists to avoid.

One exponential and one pair, both driven 80.0 mVcomputed by solving, not by drawing. The pair's characteristic is odd, so its even harmonics vanish: the second comes out at 1.1e-16 of the fundamental against 57.81% for the single stage. It is not a small residue but the floor of the arithmetic. The price is the third harmonic, 12.580% against 25.277%, and total distortion of 12.747% against 63.76%.-101-0.100-0.05000.0500.100differential drive (volts)output, normalisedthe pair: odd, and it saturatesone exponentialharmonics, as a fraction of the fundamentalsingle, h257.808%pair, h21e-16single, h325.277%pair, h312.580%single, h48.798%pair, h41e-16single, h52.531%pair, h52.056%solved, then checked — evenness measured, not assumedthe pair's second harmonic is 1e-16
Fig. 7 A differential pair and a single stage at large drive. Nothing on this page is changed by using a pair: each half has the same internal capacitances and the same Miller multiplication of the collector-base one, so the linearity argument of the previous essay and the bandwidth argument of this one are independent, and a design has to satisfy both.