A comparator's delay, at a divider ratio of 0.50
Drawn above at its default parameters, which is almost never how an essay calls it. A placement states the numbers that essay is arguing about, so the figure a reader meets is about that argument rather than about the generator — 98% of the placements on this site pass one, and the phase that raised that number from 12% found eight captions describing a figure the page was not showing.
At those defaults the edge it states is 4/(1+β) = 2.667, and it is not 2 — the right-hand slot
of the caption strip, which on this site is never used for anything else, and which is read
back out of the drawing above rather than out of the code that wrote it.
It belongs to Circuits that do a job, and the range they do it over, which is to say a change to it is a
change to lib/figures/applied.js.
It takes a slider on divider ratio β (per cent) with 5 settings,
and every one of them has passed the same assertions as the frame above — a figure whose
circuit stops doing what its caption says at any setting stops the build.
Called by 4 essays
which is the blast radius of changing it
The period a delay lengthens
Feed a comparator's output back through a resistor to the capacitor on its own input and the two thresholds stop defending a decision and start setting a period. The closed form is two RC times the log of one plus beta over one minus beta, and a marched circuit recovers it as the step shortens. A comparator that responds fifty nanoseconds late does not add fifty nanoseconds to each half cycle: it adds 4/(1+beta) times the delay to the period, 2.65 here against the 2 that counting it twice gives, because during the delay the capacitor keeps going the way it was going.
The delay that is two delays
Modelling one comparator delay applied to both transitions makes the two half cycles equal by construction, and the fix is a change of one line. Made, the duty cycle moves by 0.28 per cent for twenty nanoseconds of skew rather than the 0.40 the obvious expression gives, more hysteresis improves the duty cycle and worsens the volt-seconds at the same time, and ten nanoseconds of skew saturates a hundred-turn core in 231 cycles.
The decision taken where the ramp is slowest
A relaxation oscillator decides at its thresholds, and a threshold is the one place on a charging exponential where the slope is smallest. Noise there costs 3.399 units of period against the 2.828 that counting two crossings gives, because a draw moves the crossing it is armed for and the level the next ramp starts from. Consecutive periods share that draw, so they are positively correlated and the jitter accumulates at 3.771 per root period rather than at 3.399. And at a fixed frequency there is a best hysteresis: β = 0.648, where β·ln((1+β)/(1−β)) = 1.
The walk the core sees
Threshold noise in a relaxation oscillator walks its timing at 3.77 nanoseconds per root period at β = 0.5, because the draw two half cycles share adds. A transformer driven by the same square wave sees the difference of the halves instead, where the shared draw subtracts, and that walks at 1.89 — exactly β times the timing, 18.3 ns against 35.9 after a hundred periods over six hundred seeded runs. The per-period duty error does not vanish with the hysteresis and the walk does, consecutive duty errors are anticorrelated where consecutive periods are not, a comparator skew outruns the walk after 2(σB/d)² periods, and at a fixed frequency the core wants less hysteresis than the clock does.