Circuit Response
every model has an edge, and the figure carries it
Series

Switched-capacitor — the series

4 essays on one idea, from the one that introduces it to the one that assumes the rest.
  1. A switched capacitor is a resistor below a ratio, not below a frequency. computed by solving, not by drawing. The exact response of a capacitor shuttled between the input and a holding capacitor at 1.00 MHz — a difference equation with one pole, evaluated on the unit circle — against the continuous R–C its equivalent resistance is supposed to make. The corner is 3.15 kHz against the model's 3.18 kHz, 0.99% out, and the discrepancy is set by the capacitor ratio alone: one per cent needs a ratio under 0.0201, which is a clock 315 times the corner. The second difference has no counterpart at all — the sampled response repeats at the clock, so the image rising on the right of this plot is signal at 997 kHz arriving as though it were at the corner. The third is settling: 1 pF charged through 1 kΩ gets 500.0 time constants a half period at this clock, and being short of full charge raises the equivalent resistance by 0.000%, which puts a ceiling on the clock at 108 MHz.

    A resistor made of a clock

    A capacitor shuttled between two nodes at a megahertz behaves as a megohm, and a tenth of a picofarad shuttled at ten kilohertz behaves as a gigohm — which is how a filter with a one-hertz corner fits on a chip. What the equivalence costs is three conditions, and they bind on three different quantities: a capacitor ratio under 0.0201, a signal below half the clock, and a clock below the frequency at which the charge stops arriving.

    part 1 · filters
  2. A switched-capacitor low-pass driven past half its own clock. computed by solving, not by drawing. The clock is 1.00 MHz and the corner the earlier essay fitted is 1.59 kHz. The falling dashed curve is that continuous model, which knows nothing about a clock and goes on falling. The circles are the marched circuit, read at the frequency the output actually appears at. They part company past half the clock and by 992 kHz the model is 42.1 decibels wrong — an input just below the clock arrives just above direct current, in the middle of the passband, with the passband's own gain. The third curve is the exact discrete transfer function evaluated at the folded frequency, and it agrees with the march to 0.26 decibels, which is what says the march is measuring the folding rather than an artefact of itself.

    The filter that samples

    The rung below built a resistor out of a clock and measured two ways it is not one: a settling time, and a corner that is a capacitor ratio rather than an R–C product. Both are errors in a value and both get smaller as the design gets better. This is an error of a different kind — the arrangement is not a continuous system at all, and nothing below half the clock shows it. An input at 992 kilohertz arrives at 7.8 kilohertz with the passband's own gain, where the continuous model the rung below fitted says it is 56 decibels down.

    part 2 · filters
  3. The "offset" a switch leaves moves by 1.863 mV across a volt of signal. computed by solving, not by drawing. The charge a switch leaves on a 1 pF hold capacitor, as the input it was sampling changes. It is W·L·C_ox·(V_gs − V_th) with the clock's high level for the gate, so it falls as the input rises for two reasons at once: less gate drive, and a threshold that rises with the source potential through the body effect. The dashed line is the part that does not know what the signal is — the clock coupling through the gate overlap capacitance, -1.649 mV — and it is the only part of this that is honestly an offset. The curve stops where the switch does: an n-channel device passes nothing within a threshold of its own gate, and the model refuses rather than returning a zero.

    The offset that knows the signal

    The charge a switch leaves on the capacitor it was sampling is the gate oxide capacitance times the channel area times the overdrive, and both terms in that overdrive depend on the input — one directly and one through the body effect. So the 5.67 mV a data sheet would call an offset moves by 1.86 mV across a volt of signal, which is a gain error of 0.186 per cent and only 3.4 µV of anything else. Opening the summing-node switch first divides the gain error by the amplifier's own gain, exactly, and what is left goes from twenty-nine times the sampled-noise floor to nineteen times below it.

    part 3 · filters
  4. A stray of a tenth of the sampling capacitor moves a one-plate integrator's coefficient by 9.85%; switched at both plates, by 0.14%, nearly all of it the amplifier's own gain error. computed by solving, not by drawing. A switched-capacitor integrator with a 1 pF sampling capacitor, 4 pF of feedback and 0.5 pF at the amplifier's input, and a stray capacitance to ground at the sampling capacitor's switched plate; the error of the per-cycle coefficient against Cs/Cf, against the stray as a fraction of Cs. With one plate switched (solid) the stray is charged to the input and dumped with the capacitor, so it is part of the capacitor: the error is the stray's fraction less the amplifier's small gain error, 9.85% at a tenth. With both plates switched (dashed, A = 1000; dotted, A = 10⁵) the plate that meets the summing node moves between ground and −Vo/A, so the stray's charge carries a factor 1/A: its sensitivity falls from 1/Cf to Cs/(A·Cf²), 4000 times smaller, and what is left, 0.14%, is the amplifier's gain error (1 + (Cx + Cs)/Cf)/A, which the one-plate arrangement has as well.

    The capacitance at the switched plate

    A switched-capacitor filter's corner is a ratio of two capacitors, and every plate on a chip has a capacitance to the substrate that is on no schematic. Switch one plate of the sampling capacitor and that stray is charged to the input and dumped with it: a stray a tenth of the capacitor is a tenth of error, and a bottom plate's fifteen per cent is fifteen per cent at any size. Switch both plates and integrate into a virtual ground and the stray at the plate that meets the summing node moves only between ground and −Vₒᵤₜ/A — its sensitivity falls from 1/Cf to Cs/(A·Cf²), four thousand times less at a gain of a thousand, and what is left is the amplifier's own gain error, 0.14%. The stray has not vanished: it has moved out of the coefficient that sets the corner and into the integrator's leak, where the direct-current gain becomes A·Cs/(Cs + Cp).

    part 4 · filters

All series