The capacitance at the switched plate

A resistor made of a clock found the switched capacitor’s great advantage stated as a single equivalence: a capacitor shuttled between two nodes at a clock frequency behaves as a resistor of $1/(f_{clk}C)$, so a filter’s corner becomes the clock times a ratio of two capacitors. Ratios are what an integrated circuit is good at. Two capacitors drawn side by side on one die match to a tenth of a per cent even when each is twenty per cent off its nominal value, and a filter built from their ratio inherits the match rather than the tolerance.

The ratio in that argument is the ratio of the capacitors on the schematic. The die has more. Every plate of every capacitor sits over the substrate with an insulator between, and that is a capacitor too — about a per cent of the main one at the top plate, ten to twenty per cent at the bottom plate, which lies closest to the silicon — plus a few femtofarads of wiring at any node. None of it is drawn, none of it matches the capacitor it belongs to, and some of it is in series with the switches. The offset that knows the signal measured the charge a switch’s own channel leaves behind; this is the charge a plate’s surroundings carry along.

Whether that charge reaches the filter’s ratio depends entirely on how the capacitor is switched. Switch one plate and the stray is part of the capacitor. Switch both, and integrate into a node an amplifier holds near ground, and the stray is divided by the amplifier’s gain.

Two ways to move a charge #

The integrator is the switched-capacitor circuit’s basic block: an amplifier with a feedback capacitor $C_f$, whose inverting input — the summing node — receives a packet of charge from a sampling capacitor $C_s$ each clock cycle. Each packet moves the output by the charge over $C_f$, so the integrator’s per-cycle coefficient is $C_s/C_f$ and its equivalent time constant is $C_f/(f_{clk}C_s)$: the corner of every filter built from it is set by that ratio.

One plate switched. The sampling capacitor’s bottom plate is grounded and its top plate is switched: to the input in the first clock phase, to the summing node in the second. A stray capacitance $C_p$ at the switched plate is charged to the input along with the capacitor and dumped into the summing node along with it. The stray simply is part of the sampling capacitor, and the coefficient is $(C_s + C_p)/C_f$.

Both plates switched. In the first clock phase the left plate takes the input and the right plate is grounded; in the second the left plate is grounded and the right plate meets the summing node. The stray at the left plate is charged by the input and discharged to ground and never touches the summing node. The stray at the right plate moves between ground and the summing node — and the summing node sits at $-V_{out}/A$, which for a large gain is nearly ground too. So that stray carries charge only in proportion to $1/A$. This arrangement is the stray-insensitive integrator, and it costs two more switches than the first.

The figure shows the difference in its plainest form. With one plate switched the error is the stray’s fraction of the capacitor — 9.85 per cent at a stray of a tenth, the tenth less a small gain error the amplifier adds in both arrangements. With both plates switched it is 0.14 per cent at the same stray and 0.14 per cent with no stray at all: the curve is flat until the stray is comparable with the capacitor, and what it is flat at is the amplifier’s own gain error. A better amplifier lowers the whole curve, to 0.0014 per cent at a gain of $10^5$, and lowers the one-plate curve not at all.

The charge at the summing node, conserved #

The coefficient comes from one equation, and it is worth writing because the stray’s place in it is the whole argument. During the second phase the summing node is an isolated conductor: whatever charge it held at the end of the first clock phase, plus whatever the arriving plate brings, must be the charge it holds once the amplifier has settled. With the summing node at $V_x = -V_o/A$ and the input capacitance of the amplifier $C_x$, the two-plate integrator obeys

$$V_o[n]\left(C_f + \frac{C_f + C_x + C_s + C_p}{A}\right) = V_o[n-1]\left(C_f + \frac{C_f + C_x}{A}\right) + C_s V_{in}[n],$$

and the one-plate integrator the same with $C_s + C_p$ in place of $C_s$ in both places and the sign of the input term reversed. Read off it: in the two-plate integrator $C_p$ appears only divided by $A$, alongside $C_x$ and $C_s$, in the correction to the coefficient’s denominator. In the one-plate integrator it appears undivided in the numerator.

Differentiating the coefficient with respect to the stray gives the sensitivities directly: $1/C_f$ for one plate switched, $C_s/(A C_f^2)$ for two. With a 4 pF feedback capacitor and a gain of a thousand, the second is four thousand times the smaller.

The closed form above was derived once, by hand. The figure’s lines were not: each capacitor is held as a pair of plate voltages, the first clock phase sets the plates that are switched to a source, the second solves for the one floating node’s voltage that conserves its charge with the amplifier holding $V_o = -AV_x$, and nothing in that bookkeeping forms either coefficient. The two routes agree to $2\times10^{-14}$ V over four hundred cycles. With 0.3 pF of stray, the one-plate integrator moves 3.245 mV in its first cycle for 10 mV in, 29.8 per cent more than the design’s 2.500; the two-plate integrator moves 2.496, 0.16 per cent less, which is its gain error.

A gain error that does not care about the stray #

The two-plate integrator’s remaining error is the amplifier’s, and the stray is a small term inside it.

The two-plate coefficient error is $(1 + (C_x + C_s + C_p)/C_f)/A$ to a per cent at every gain above a thousand. At a gain of ten thousand it is 0.0116 per cent with no stray and 0.0137 with a stray as large as the sampling capacitor itself — a stray the size of the capacitor costing two thousandths of a per cent. The one-plate integrator with a 0.3 pF stray sits at 30 per cent at every gain on the figure, because its error has nothing to do with the amplifier.

That reframes what the switched capacitor’s ratio accuracy depends on. In the one-plate arrangement it depends on layout: how much stray each switched plate carries, and whether it matches between the capacitors whose ratio matters — which it does not, since a stray depends on a capacitor’s perimeter and its surroundings rather than its area. In the two-plate arrangement it depends on the amplifier’s gain, a single number common to every integrator in the filter, which a designer can buy. The average an integrator can hold found the same gain setting how long such an integrator can average before its leak stops it; here it sets how accurately it integrates at all.

Small capacitors, fixed strays #

The stray’s fraction is not a constant, because part of it does not scale with the capacitor. Wiring, a switch’s own junctions and the edge of the plate contribute a few femtofarads at a node whatever the capacitor’s area, and the small capacitors that low-frequency filters need are exactly where that matters.

With 2 fF of wiring at the switched plate and the top plate switched — the right orientation for the one-plate circuit — the error is $0.002 + 2\,\text{fF}/C_s$: 20.2 per cent at a 10 fF capacitor, crossing 1 per cent at 250 fF, and 0.22 per cent at 10 pF. Switch the bottom plate by mistake and the error is never below 15 per cent. With both plates switched, and the bottom plate’s whole stray included, it is 1.36 per cent at 10 fF and 0.13 per cent at 10 pF; at the small end what remains is the amplifier’s half-picofarad of input capacitance against a feedback capacitor that has shrunk with everything else, since $C_x/C_f$ enters the gain error directly.

A resistor made of a clock built a one-hertz corner from a tenth of a picofarad shuttled at ten kilohertz. At 100 fF the one-plate integrator is 2.2 per cent off with its top plate switched and 17 per cent with its bottom plate; the two-plate integrator is 0.25 per cent off. The ratio-accurate low-frequency filter that the equivalence promised needs the two extra switches.

Where the stray goes instead #

A charge that does not arrive in the coefficient has to go somewhere, and the conservation equation says where: the stray at the plate that meets the summing node is also in the coefficient of $V_o[n]$ on the left, and nowhere else.

The leak — the fraction of its state an integrator with finite gain loses each cycle — is the same in both arrangements: $(C_s + C_p)/(AC_f + C_f + C_x + C_s + C_p)$, so the integrator remembers 4,001 cycles with a stray of a thousandth and 1,858 with a stray equal to the capacitor. In both, the stray at the summing node discharges into the leak. What differs is the direct-current gain. The one-plate integrator has the stray in its coefficient too, so the two cancel and its gain at direct current stays at $A$. The two-plate integrator does not, and its gain at direct current falls to $A\,C_s/(C_s + C_p)$ — 464 at a gain of a thousand with a stray equal to the capacitor.

So the stray has been moved rather than removed: out of the ratio that sets the filter’s corner, which every filter cares about, and into the leak, which only an integrator meant to integrate for thousands of cycles cares about. That is a good trade for a filter. It is a worse one for the averaging integrator of the average an integrator can hold, whose floor was set by exactly this leak: there the leak capped the average at $2AC_f/C_s$ cycles, and a stray on the summing-node plate shortens that cap by the factor $C_s/(C_s + C_p)$.

What a filter does with a wrong coefficient #

An integrator’s coefficient is a filter’s frequency. A first-order lowpass built from one integrator and a damping capacitor has its corner at the clock times the coefficient over $2\pi$, so a coefficient 9.85 per cent high is a corner 9.85 per cent high, and the passband edge the designer specified is somewhere else. The filter that samples found the sampled circuit’s own corner already below the continuous model’s by a computable amount; a stray adds an error of a different kind, because it is not computable from the schematic — it is whatever the layout made it.

A second-order section is worse placed, because it is built from two integrators and its quality factor is a ratio of their coefficients and a damping coefficient. If every switched plate in the section carried the same fractional stray the frequency would move and the Q would not, since the strays would cancel in the ratio. They do not carry the same stray: a capacitor’s stray goes with its perimeter and its neighbours, a small damping capacitor has proportionally more perimeter than a large integrating one, and the plates sit at different distances from the wiring. So a one-plate section’s Q is off by the difference of fractional strays between its capacitors — exactly the quantity a ratio-matched layout does nothing about. The two-plate section’s Q error is the difference of two gain errors that share one amplifier gain, which nearly cancels.

The same move, made elsewhere #

Making a stray carry no charge by holding both of its plates at the same voltage is not a switched-capacitor invention. It is the guard ring. The current that does not reach the input surrounded a high-impedance input with a conductor driven to the input’s own potential, so that the leakage resistance and the stray capacitance between them had no voltage across them and carried nothing. The two-plate integrator’s summing-node plate does the same thing in time rather than in space: in each phase the plate connects to a node that is at, or within $V_o/A$ of, ground, so its stray to the substrate never sees a voltage change and never moves a charge.

And the guard’s limitation is the same one. A guard is only as good as the follower driving it, and the sign of what the guard gives back found that an imperfect follower turns a guarded capacitance into a small residual of the wrong sign. Here the “follower” is the amplifier holding the summing node at $-V_o/A$, and the residual is the $C_p/A$ in the gain error. In both places a stray is not removed; it is divided by how well something else holds a voltage still.

What the two extra switches cost #

The two-plate arrangement has four switches where the one-plate arrangement has two, and switches are not free. Each one that opens on the sampling capacitor leaves a channel’s charge behind, which the offset that knows the signal measured as an offset that depends on the signal; each one that closes and opens samples its own resistance’s noise, the $kT/C$ that the noise a clock does not make found independent of the clock and the resistance. The two-plate integrator samples noise in both of its phases, which the average an integrator can hold wrote as $2kT/C_s$ a cycle.

There is also a sign. The two-plate integrator with this phasing does not invert: the right plate was grounded while the left took the input, so the charge it brings to the summing node is $-C_sV_{in}$ and the output moves by $+C_sV_{in}/C_f$. Swapping which plate is grounded in which phase makes it inverting, with the same insensitivity, which is why the arrangement is usually drawn with both phasings available: one capacitor and four switches give either sign of coefficient with no stray in it, something the one-plate circuit cannot do at all.

The ratio, and what it is the ratio of #

The switched-capacitor filter was sold on a ratio of capacitors. With one plate switched it is a ratio of capacitors-plus-strays, and the strays neither match nor scale: a tenth of stray is a tenth of error, a bottom plate’s fifteen per cent is fifteen per cent at any size, and 2 fF of wiring is 1 per cent at 250 fF. With both plates switched it is a ratio of capacitors corrected by the amplifier’s gain error, $(1 + (C_x + C_s + C_p)/C_f)/A$ — 0.14 per cent at a gain of a thousand, nearly independent of the stray — and the stray has moved into the integrator’s leak, where it lowers the direct-current gain to $A\,C_s/(C_s + C_p)$.

Still open: the summing node’s own stray, a gain that depends on the output, and settling with the stray in it #

The summing node’s stray. The amplifier’s input capacitance $C_x$ sat in the gain error at 0.5 pF and dominated it for small feedback capacitors. A real summing node also carries the switches’ junctions and the wiring of every input that feeds it, and in a filter several integrators’ inputs share nothing but their amplifiers. How the gain error grows with the number of inputs on one summing node, and whether it ever overtakes a careful one-plate layout, is a comparison this essay’s figures suggest and do not draw.

A gain that depends on the output. The analysis treats $A$ as a constant. A real amplifier’s gain falls as its output approaches a rail, so the two-plate integrator’s coefficient error grows with the signal — a distortion, of the kind how small is small signal measured for a junction, with the stray still divided by a gain that is no longer constant.

Settling with the stray present. Every coefficient here assumes the amplifier settles completely in each phase. A stray at the summing node loads the amplifier and slows that settling, and the one-plate arrangement’s stray, which arrives through a switch, does so differently from the two-plate one’s. Which arrangement settles first, at a given amplifier, is the measurement that would put a clock rate on the trade.