Circuit Response
every model has an edge, and the figure carries it
Series

Regulator — the series

9 essays on one idea, from the one that introduces it to the one that assumes the rest.
  1. A five-volt regulator's output impedance, with 1.00 Ω of series resistance. 0.430 mΩ at direct current, 1.95 Ω at 10.0 kHz — a factor of 4.52e+3 — and it has already doubled by 4.81 Hz. The upper curve is the same circuit with its loop opened, and the ratio between them is the loop gain. A regulator is a voltage source below a frequency and the datasheet's milliohms are the value at the bottom of it.

    A source below a frequency

    A five-volt regulator's output impedance is 0.43 milliohms, which is the number a datasheet quotes. It has doubled by 4.8 hertz, is ten times worse by 27, and reaches 1.95 ohms at ten kilohertz — four and a half thousand times its own specification, and higher there than the same circuit with its feedback loop cut. Two routes to that curve, sharing only the netlist, agree to a part in ten to the thirteenth.

    part 1 · applied
  2. The window a 10 µF capacitor leaves. Above 939 mΩ the loop holds 45° of margin; below it the regulator rings and then oscillates. The droop after a 100 mA step is smallest at 817 mΩ — 129 mV — and by 19.9 Ω it is 1.468 V, because at the first instant of a step the capacitor cannot move and the whole step falls across its series resistance. Two requirements, opposite directions, and the useful values are between them.

    Two requirements pulling one capacitor

    The output capacitor's series resistance is a stability requirement and a transient requirement at once, and they pull it in opposite directions. Below 939 milliohms this loop has less than 45 degrees of margin; above about 850 the droop after a load step starts to grow, because at the first instant of a step the capacitor cannot move and the whole step falls across that resistance. The droop is smallest 10 per cent inside the unstable region, which means the best transient this design can have is one it must not be built with.

    part 2 · applied
  3. Rejection is not a property of the loop. The same regulator with the same loop gain and the same 46.5° of phase margin, drawn twice. With the amplifier's output referred to ground the rail reaches the output at -67.3 dB at the bottom and 5.79 dB at 10.0 kHz — where it is amplified. Referred to the rail instead, every point is 60.00 dB lower, which is 20 log(gm·ro) for the pass device and not a design choice.

    What gets through from the rail

    A regulator's job is to hold its output still while its input moves, and the measurement says it does that well at ten hertz, badly at a kilohertz, and not at all at ten kilohertz — where this one puts out 1.9 times what arrives. Then the same netlist with one node moved, the same loop gain and the same 46.5 degrees of margin, rejects 60.009 decibels better at every frequency in six decades. The sixty decibels is the pass device's own intrinsic gain and it is not a design choice.

    part 3 · applied
  4. The ripple 1000 µF leaves, through the regulator: 60.62 mV rather than 21.11 mV. One settled cycle of the reservoir's output — 1.331 V peak to peak across 1000 µF — split into 1000 Fourier lines, each passed through the solved regulator's rail-to-output response, and summed. The output is 60.62 mV peak to peak. The ripple times the rejection at 100 Hz, -36.00 dB, gives 21.11 mV, which is 2.872 times too little: the rejection worsens at twenty decibels a decade, so each harmonic of the sawtooth arrives at nearly the size of the first. The 100 Hz line carries 23.4% of the output's mean square and the lines above 1 kHz 10.4%; the first three arrive at 7.731 mV at 100 Hz, 7.200 mV at 200 Hz, 6.388 mV at 300 Hz. The dashed curve is the 100 Hz line alone.

    The ripple that arrives as a comb

    The rejection essay multiplied two numbers: 1.331 volts of reservoir ripple and the regulator's 36.0 decibels of rejection at a hundred hertz, for 21 millivolts at the output. The ripple is a sawtooth, a comb of lines at every multiple of a hundred hertz, and the rejection worsens at twenty decibels a decade — so the second line arrives at nearly the size of the first, and the third too. Summed with their phases, the output is 60.62 millivolts, 2.87 times the estimate, and the hundred-hertz line carries only 23.4 per cent of it. A reservoir twenty-one times larger cuts the rail's ripple 14.8 times and the regulated ripple 5.95.

    part 4 · applied
  5. The capacitor across the upper resistor: 90.9° of margin at 836.5 pF, and less ripple past it. The regulator's phase margin against a capacitor across the upper divider resistor, with the output ripple the 1000 µF reservoir leaves beside it. With no capacitor the margin is 46.47° at a crossover of 9.73 kHz, the output impedance at 10 kHz is 1.95 Ω, the worst rail rejection is 5.79 dB and the ripple 60.62 mV. The margin is greatest, 90.929°, at 836.5 pF — a zero at 6.34 kHz and a pole at 25.4 kHz around a crossover moved to 16.9 kHz — where the output impedance at 10 kHz is 828 mΩ, the worst rail rejection -1.50 dB and the ripple 52.33 mV. At 10 nF the margin has fallen back to 66.34° and the ripple is 35.40 mV.

    The capacitor across the upper resistor

    The rejection essay said a regulator reproduces its reference times its divider's four, and that a capacitor across the lower divider resistor brings that down to one at high frequency. Measured, the loop peaks the reference's gain to 5.68 near its crossover before any capacitor is added; a nanofarad across the lower resistor raises the peak to 11.2; and the capacitor that brings it down belongs across the upper resistor, where a nanofarad keeps the gain from ever exceeding four. The same capacitor is a lead pair in the loop: 836.5 picofarads takes the phase margin from 46.5 to 90.9 degrees, and ten nanofarads, past that optimum, still holds 66 while cutting the output ripple from 60.6 millivolts to 35.4.

    part 5 · applied
  6. A capacitor across the upper divider resistor removes the output capacitor's resistance floor. computed by solving, not by drawing. Two series resistances against the capacitance across the upper divider resistor: the smallest the loop tolerates at 45° of margin (lower curve), and the one that gives the smallest droop after a 100 mA load step (upper). With no capacitor they are 939 mΩ and 885 mΩ — the second BELOW the first, which is the conflict this design has: the best transient is one the loop refuses. The floor falls as the capacitor grows and between 500 and 836.5 pF it leaves the sweep altogether, so every series resistance down to a milliohm is stable. Past about 5000 pF the floor climbs back and overtakes the optimum again. The shaded band is where the design a transient wants is one the loop allows.

    The floor a second capacitor removes

    Two requirements pulling one capacitor found a regulator whose best transient is one it must not be built with: below 939 milliohms of output-capacitor series resistance the loop has under 45 degrees of margin, and the droop is smallest at 885. The capacitor across the upper divider resistor, added for the reference's sake, dissolves that conflict. At 836.5 picofarads the 45-degree floor leaves the sweep entirely — every series resistance down to a milliohm is stable — and the droop falls 40 per cent at the same time. The band of capacitances that do it runs from 100 picofarads to 5 nanofarads, and above it the conflict returns.

    part 6 · applied
  7. Losing capacitance to bias raises this loop's margin; the corner that binds is the ceramic at full value. computed by solving, not by drawing. Phase margin of the five-volt regulator with a 5.00 mΩ ceramic output capacitor, against the capacitance that capacitor keeps at the working voltage, from the full 10 µF down to 1.5 µF, for five capacitors across the upper divider resistor. With none, the margin climbs from 18.0° at full value to 43.6° at 15% kept, so the lost capacitance is stabilising rather than the reverse. 630 pF holds at least 49.7° across the whole range. 836.5 pF, the value that removed the resistance floor at the nominal capacitance, gives 48.8° at full value and 44.3° at 15%: the capacitor that has lost the most is the one it fails on.

    The capacitance the bias takes away

    A ceramic output capacitor has a few milliohms of series resistance, which a capacitor across the upper divider resistor made legal, and a capacitance that falls with the voltage across it — a ten-microfarad part at five volts is two microfarads to a small signal. Swept from the full ten down to that fifth, the regulator's margin does not collapse. It rises: with no divider capacitor from 18.0° to 38.5°, because the output pole climbs away from the amplifier's. The corner that binds is the capacitor at full value. One divider capacitor, 423 to 808 pF, holds 45° at every capacitance between. The 836.5 pF that removed the resistance floor sits just above that band, and the lost capacitance is paid for in droop: 103 mV at full value, 202 mV at a fifth.

    part 7 · applied
  8. At full capacitance the margin falls with the load, and below a tenth of an ampere no divider capacitor gets it past 36.9°. computed by solving, not by drawing. Phase margin of the five-volt regulator with a 5 mΩ ceramic keeping 10 µF, against the load current from 5 mA to 1 A, for four capacitors across the upper divider resistor. 630 pF, which held 45° at every capacitance at an ampere, gives 49.7° at 1 A and 36.0° at 5 mA. With no capacitor the margin at 5 mA is 0.1°. The dotted level is 36.87°, the most phase a zero and a pole four times apart can ever lead by, and every curve ends under it. The crossover stays between 12.9 kHz and 13.2 kHz over the whole range.

    The lead a divider can give

    At an ampere one capacitor across the upper divider resistor holds this ceramic regulator above 45° at every capacitance the part keeps. At 5 mA nothing does. The crossover stays at 13 kHz while the output pole falls from 3.20 kHz to 31.8 Hz, so the loop arrives at unity with every lag it has and the only phase left is the lead the divider capacitor makes — and that lead has a ceiling, arcsin((G − 1)/(G + 1)), set by the divider's ratio alone. For a five-volt output from a 1.25 V reference it is 36.87°, and the best capacitor reaches 36.83°. Over the rectangle from 5 mA to an ampere and ten microfarads to two, the best single capacitor gives 32.4°. Putting 416 mΩ back in series with the ceramic restores 45° over all of it, and lowers the droop rather than raising it.

    part 8 · applied
  9. The droop of the ceramic regulator against the rise time of a 100 mA load, with the capacitor at full value, half and a fifth. computed by solving, not by drawing, marched from the operating point: 10 µF, 5 mΩ of series resistance, 630 pF across the upper divider resistor, the 100 mA arriving as a straight ramp. A step droops 103 mV at 100%, 137 mV at 50%, 203 mV at 20% of the capacitance. A ramp of a millisecond droops 2.98 mV, 2.56 mV, 2.56 mV, and the slowest ramps approach the loop's inductance, 25.2 µH, times the ramp's rate (dashed) — a quantity with no capacitance in it — times 1.18, 1.03, 1.03, the share the loop's ringing adds. The full-value and fifth-value curves cross at 23 µs; slower than that, the larger capacitor droops more.

    The load that rises slower than the loop

    Every droop a regulator is sized against is a load step with an infinitely fast edge, and a ceramic regulator droops 103 millivolts on its full 10 µF and 203 on a fifth of it. Give the same 100 mA a rise time and the ordering does not survive: past 23 microseconds the full capacitor droops more than the fifth, and a slow ramp's droop is the loop's own 25.2 µH times the load's rate of change — a number with no capacitance in it, raised 18 per cent on the full capacitor by the impedance peak its slower loop leaves. For a 10 mV budget the load must take 298 µs to arrive on the full capacitor and 253 on the fifth.

    part 9 · applied

All series