The capacitance the bias takes away

Two requirements pulling one capacitor found that this five-volt regulator needs more than 939 milliohms of series resistance in its output capacitor to hold 45 degrees of phase margin. That is a specification an electrolytic meets and a ceramic misses by two orders of magnitude. The floor a second capacitor removes put 836.5 pF across the upper divider resistor and watched the floor leave the sweep: every series resistance down to a milliohm was stable, so the ceramic became a buildable choice.

That essay ended on the catch. A ceramic’s capacitance is not a constant. The capacitance that is not one number measured a ten-microfarad class II part at its rated five volts and found it 2.000 µF as a slope, which is the capacitance a small signal sees and the one a loop’s stability depends on. At zero bias the same part is its full ten. So the regulator’s output capacitor is a fifth of its printed value while the regulator is doing its job, and its full value while the output is still rising at turn-on. The question left open was whether the band of divider capacitances that made the ceramic legal stays open across that range.

The margin rises as the capacitance falls #

Every figure on this page is at 5 mΩ of series resistance, which is a ceramic’s own, with the output capacitor’s capacitance taken as the fraction of its nominal ten microfarads it keeps. Nothing else about the regulator moves: the same 1.25 V reference and 30 kΩ over 10 kΩ divider, the same 5 Ω load, the same pass device, the same error amplifier with its pole at 15.9 Hz.

The expectation going in was that losing capacitance would be a loss of stability, since it is a loss of the component that holds the output still. The measurement says the opposite. With no divider capacitor the margin climbs steadily as the capacitance falls, from 18.0° at the full ten microfarads to 38.5° at two and 43.6° at one and a half. The loss of capacitance is stabilising.

The reason is where the output capacitor puts its pole. The loop has two low poles: the error amplifier’s, at 15.9 Hz, and the output node’s, where the capacitor meets the 5 Ω load, at about 3.2 kHz with ten microfarads. Two poles close together are what give a loop its phase trouble, since their lags add near the crossover. Taking capacitance away moves the output pole up — to about 16 kHz at two microfarads — and so moves it away from the amplifier’s. The crossover follows it up, but not as fast, and the loop arrives at unity gain with less of the second pole’s lag accumulated. A loop with poles further apart has more margin, and losing capacitance pushes them further apart.

An electrolytic’s large series resistance would have helped here too, by adding a zero near the crossover that cancels the output pole’s lag; that is the whole story of the resistance floor. A ceramic’s 5 mΩ puts that zero at about 3.2 MHz with ten microfarads, which is far past anything the loop does. So the ceramic’s loop has no lead of its own, and whatever lead it gets has to come from the divider capacitor.

Where the lead goes #

A capacitor across the upper divider resistor is a lead pair. It puts a zero at $1/(2\pi R_1 C_{ff})$ and a pole at $1/(2\pi (R_1 \parallel R_2) C_{ff})$, four times higher here since $R_1$ is three times $R_2$, and the phase it adds is greatest at the geometric mean of the two. At 630 pF that is a zero at 8.4 kHz, a pole at 33.7 kHz and the peak of the lead at 16.8 kHz. The lead helps most when that peak sits on the crossover, and the crossover is what the lost capacitance moves: 12.9 kHz with the full ten microfarads and 630 pF across the divider, 37.5 kHz at two.

So the best divider capacitor ought to move with the ceramic’s capacitance. As the capacitance falls and the crossover rises, the lead’s peak should follow it up, which means a smaller divider capacitor.

It does. The best divider capacitor falls from 708 pF at the full ten microfarads to 282 pF at two, and the whole band of capacitances that hold 45 degrees slides down with it. What matters for a design is that the bands overlap. Every band from full value down to a fifth contains 423 to 808 pF, and that shared strip is set by two different corners. Its floor comes from the full capacitor: at ten microfarads nothing below 423 pF supplies enough lead, since the crossover is low and a small capacitor puts its lead too high. Its ceiling comes from the smallest capacitance: at two microfarads anything above 808 pF puts the lead’s pole below a crossover that has risen to meet it, and the element starts to lag.

836.5 pF, the value that removed the resistance floor, is just above that ceiling. At the ceramic’s nominal value it is a good choice, 48.8 degrees; at a fifth it gives 44.2, below the line it was chosen to hold. It was chosen, correctly, for a capacitor that did not move, and the ceramic moves exactly the way that takes it out of the band.

The choice that holds everywhere #

A designer who knows the capacitance will range from ten microfarads at turn-on down to two in service should choose the divider capacitor for the worst margin over that range, not for the margin at either end.

The worst-case curves have a shape that makes the choice easy. Below the best value they are one curve: for any divider capacitor small enough, the worst case is always the full capacitor, whatever range is allowed, because there the full capacitor is the one short of lead. Above the best value they part, since a large divider capacitor overshoots the crossover of a small output capacitor, and a wider range of capacitance exposes more of that. The best choice for the whole range from ten microfarads to two is 649 pF, and it gives 49.8 degrees in the worst case — the same 49.8 that 713 pF gives when only the full capacitor is considered. Allowing for the lost capacitance costs three hundredths of a degree at the corner that binds.

That is an unusually cheap robustness. It exists because the two corners fail on different sides of the best value: the full capacitor limits a small divider capacitor, the small one limits a large divider capacitor, and between them there is room. A design can be centred in that room at almost no cost, and the one that is not centred — 836.5 pF, chosen for a fixed capacitor — gives 44.2 degrees at the far end of the range, five and a half below the centred choice.

The instinct to add capacitance #

The result has an uncomfortable corollary. If the full capacitor is the hard case, then more capacitor is a harder one, and the usual repair for a regulator that rings — a larger output capacitor — makes this one worse. With 649 pF across the divider the margin is 49.8 degrees at ten microfarads, 45.7 at fifteen, 40.9 at twenty-two and 30.7 at forty-seven. Each added microfarad lowers the output pole towards the amplifier’s and lowers the crossover below the divider’s lead, and both cost phase. Without the divider capacitor the same trend runs from 18.0 degrees at ten microfarads to 8.7 at forty-seven.

So this loop wants an upper bound on its output capacitance rather than a lower one, and that bound has to be stated for the capacitance at zero bias, since that is the largest the part will ever present. A designer who fits a 22 µF ceramic because a 10 µF one lost four-fifths of itself has fixed the droop and spent nine degrees of margin at turn-on, where the output is still low and the capacitor is at its full value. The protection is to choose the divider capacitor for the largest capacitance that will be fitted and check the smallest, rather than the reverse.

The ceramic’s own resistance changes nothing #

A ceramic’s series resistance is not a single number either. It varies between parts and with frequency, from a couple of milliohms to a few tens. The hero figure’s slider covers 2 to 20 mΩ, and across that range 630 pF keeps between 49.5 and 50.3 degrees at its worst point, while 836.5 pF moves from 48.6 to 49.6 at full value and from 44.2 to 44.6 at the low end. The resistance’s zero is at 3.2 MHz with 5 mΩ and ten microfarads, and still at 800 kHz with 20 mΩ, which is well above any crossover this loop reaches. The loop cannot see the resistance, so the band found here does not depend on it — which is the reason a divider capacitor was the right tool for a ceramic in the first place.

Where the lost capacitance is paid for #

The capacitance does not vanish without cost. It is simply not paid for in stability. The load step is where it shows.

The droop after a hundred-milliamp step rises from 103 mV with the full capacitor to 202 mV at a fifth. It does not rise five times, only 1.96, and the reason is the rising crossover again. For the first moments after a step the loop has not answered and the capacitor holds the output alone; the loop arrives on the time scale of its crossover. A capacitor holding a step current $\Delta I$ for about a radian at the crossover frequency $f_c$ sags by about $\Delta I/(2\pi f_c C)$. That estimate is the dashed line — 123 mV at full value and 212 at a fifth — and it follows the marched droop within a fifth everywhere. The capacitance fell fivefold, the crossover rose nearly threefold, and the droop is the quotient.

With a ceramic’s few milliohms the first instant of the step contributes nothing measurable. It is half a millivolt at 5 mΩ. The first requirement of two requirements pulling one capacitor, which put the whole step across the series resistance at the first instant, has gone with the resistance. What is left is the capacitor’s own charge against the loop’s speed, and the lost capacitance halves the one while the loop only partly recovers it through the other.

The traces make the trade visible. At a fifth of its capacitance the output drops twice as far and comes back faster, in 37 µs against 80, because its loop crosses over nearly three times higher. Both overshoot once and settle, as a loop with about fifty degrees of margin does. So the bias costs depth and not time. For a load that cares about the size of a dip, such as a logic rail with a tight tolerance, the design has to be sized against the two microfarads, not the ten. For a load that cares about how long the rail is disturbed, the smaller capacitance is no worse.

What a designer should take #

Choose a ceramic’s divider capacitor for the whole range its capacitance will cover, and expect the worst margin at the full value, which is the capacitor at low bias. With this regulator at full load that range from ten microfarads down to two is served by anything from 423 to 808 pF, with 649 pF the centre; at light load it is not, and that corner is still to be solved. Size the droop budget against the capacitance at the working voltage, a fifth of the nominal here, and do not count on the full value for transients.

The broader lesson is about which direction a parameter’s variation is dangerous in. A ceramic’s capacitance loss is usually treated as a hazard to stability, and for a regulator whose stability came from the output capacitor’s series resistance that was the right instinct: less capacitance moved the resistance zero up and away from where it was needed. With the lead supplied by the divider instead, the capacitance loss moves the output pole the helpful way. What the variation does depends on what the loop was leaning on, and what gets through from the rail and the capacitor across the upper resistor both found the same thing from other directions: the parts of this regulator that look independent are one loop.

How the numbers were obtained #

The regulator is the same netlist as a source below a frequency: a transconductance error amplifier with its own output resistance and a 15.9 Hz pole, a driver resistance and gate capacitance, a pass device of one siemens with a kilohm of output resistance, the divider, the load, and the output capacitor as a capacitance in series with its resistance. The loop is broken at the error amplifier’s input, where breaking it is exact because a transconductance draws no current, and the phase margin is found at unity return ratio. The band edges are bisected in log capacitance from a 49-point grid, twenty-six iterations each. The droop is marched from the direct-current operating point, so that what is drawn is the step and not a turn-on, over 4 ms in 6000 steps, with the step applied at 0.2 ms.

What it leaves out #

The capacitance is a constant at each point of each sweep. A real ceramic’s small-signal capacitance depends on the instantaneous voltage, so during a droop of 200 mV the capacitance itself moves by a little, and during turn-on it moves through the whole range. Neither changes a margin measured about an operating point; both change the shape of a large transient, and the second is a figure of its own.

Temperature. The coefficient that is about one reading found a class II ceramic’s printed temperature coefficient to describe one bias condition only. The range swept here, a factor of five, is wider than temperature usually moves a biased part, so the band found above should cover it, but the combination of bias and temperature has not been solved.

The load, and it matters more than anything else left out. Every loop here drives 5 Ω, an ampere at five volts. Solved at 50 Ω with the same 649 pF, the margin is 37.6 degrees at ten microfarads and 29.2 at two — below the line at both ends, and with the order reversed, so that at light load the biased capacitor is the harder case rather than the full one. The whole argument above is a statement about full load. A regulator that must hold its margin from an ampere down to a few milliamps has a corner this page has not solved, and it is probably the one that binds.

And the reference’s noise, which the divider capacitor also shapes, and which the ripple that arrives as a comb and its successors left as a gain rather than a voltage.

Still open: the light load, the turn-on, and the load that is not a step #

The light load. At 50 Ω the robust divider capacitor holds 37.6 degrees at full capacitance and 29.2 at a fifth, so the band that serves every capacitance at an ampere does not exist at a tenth of one. The load’s resistance moves the output pole just as the capacitance does, and the question is whether any single divider capacitor serves the rectangle of both — load from a few milliamps to an ampere, capacitance from ten microfarads to two — or whether a ceramic regulator of this topology needs a minimum load, or a second lead, to be stable across it.

The turn-on. At turn-on the output rises from zero and the ceramic’s capacitance falls from its full value to a fifth as it does. The regulator therefore passes through every point of the range swept here in a few hundred microseconds, and the full-value corner, which is the one that binds, is exactly where it starts. Marching a turn-on with a capacitance that follows the voltage would say whether the overshoot at the end of the ramp belongs to the full capacitor or the biased one.

The load step that is not a step. With the series resistance gone, the droop is the capacitor against the loop’s speed. A load whose current rises over a time comparable to the loop’s own, a few tens of microseconds here, should droop by less than either figure above, and there is a rise time at which the capacitance stops mattering because the loop keeps up. Finding it against the kept capacitance would say how much of the droop budget a slow load can give back.

The reference’s noise, through the robust divider capacitor. 649 pF was chosen for margin across the capacitance range. The same capacitor sets the reference’s gain to the output above the lead’s zero, and a smaller capacitor moves that zero up. Integrating a reference’s density through the loop at both ends of the range would say whether the robust choice costs anything in noise, or whether, like its margin, it is nearly free.