Circuit Response
every model has an edge, and the figure carries it
Lines, where a wire has a length

The resistor at the wrong end

A lattice diagram is read at the two ends of a line, and that is where the two respectable terminations look identical: a clean step, one delay late, at the receiver. Anyone standing halfway along a series-terminated net sees half the swing held for a full round trip, which for a logic input is not a level at all. The interval is 2(1−x) delays exactly, it is zero only at the far end, and the scheme that never has it draws sixty milliamperes for as long as the level is held.
16 min read 8 figures The schematic is a labelEvery model has an edgeMeasured, not tabulated

Assumes: The staircase in time · A ladder is not a line

The staircase this field opens with is read at two places: the source end and the load end. That is where a lattice diagram is drawn, it is where a measurement is usually taken, and it is where two of the three ways of terminating a net look like the same thing.

No termination. A driver with a low output impedance and an open far end. The launched wave is most of the swing, the open end doubles it, the low-impedance source reflects it back inverted, and the answer rings: 82 per cent overshoot at the load, settling over several round trips.

A series resistor at the source, chosen so that the driver’s output impedance plus the resistor is the line’s characteristic impedance. The launched wave is exactly half the swing by construction; the open far end doubles it to the full swing; the returning wave arrives at a matched source and is absorbed. One clean step at the receiver, one delay late, no ringing, and no static current at all.

A parallel resistor at the load, making the far end look like the line. Nothing reflects. The wave is right everywhere the instant it arrives, and the line carries the level’s current for as long as the level is held.

Read at the ends, the second and third are both correct and only one of them costs power, so the series resistor is free. It is free only for a receiver at the end of the line.

A series-terminated net holds half a swing for 1.0 delays at 50% along itcomputed by solving, not by drawing. What a receiver 50% of the way along one net sees under three terminations, from a lattice evaluated at that point rather than at the ends. The shaded strip is the interval in which a logic input has no defined answer — between 30% and 70% of the swing. The series-terminated net sits in it for 4.83 ns, which is 2(1 − x) delays exactly and is zero only at the far end; the unterminated net sits in it for 4.83 ns and then overshoots by 82%; the parallel-terminated net never does, and draws 60 mA down the line for as long as the level is held.024601020time (nanoseconds), with one delay = 4.83 nsvoltage at the receiver (volts)1.00 delays undefinedunterminated, parallel, and seriesreceiver at50% of the netone delay4.83 nsseries: undefined for4.83 ns…which is1.00 delaysparallel: undefined for0.00 ns…static current60.0 mAnone: undefined for4.83 ns…and overshoots by81.8%series static current3.3 nAsolved, then checked — one lattice, read between the ends1.00 delays at 50% along
Fig. 1 What a receiver halfway along one net sees under the three schemes. The shaded strip is where a logic input has no defined answer; the series-terminated net sits in it for a full round trip and the parallel-terminated one never does.

The lattice, read between the ends

The generalisation is one line and it is the whole essay.

A wave launched at the source arrives at a fractional position xx along the line at xTdx T_d. The wave reflected from the far end passes the same point on its way back at (2−x)Td(2 - x)T_d. Those are different times, so anybody standing between the ends sees the two arrivals separately, and what they see in between is whatever the first wave alone amounts to.

For a series-terminated net the first wave is half the swing, by construction, and it is meant to be: the far end doubles it. So an interior receiver sits at half the supply for

(2−x)Td−xTd=2(1−x)Td(2 - x)T_d - xT_d = 2(1 - x)T_d

Measured, at a metre of line with a delay of 4.834 nanoseconds: 1.798 delays at a tenth of the way along, 1.500 at a quarter, 1.000 at halfway, 0.502 at three quarters, 0.200 at nine tenths, and zero at the end. The expression and the measurement agree to the third decimal at every position, and the zero at the end is the reason the scheme has a good reputation.

The other way to read the same expression is as a statement about the round trip from the receiver to the far end and back, which is what 2(1−x)Td2(1-x)T_d is. A receiver’s interval is set by how far it is from the far end, not by how far it is from the driver, and that is worth having as a rule because it inverts the intuition: moving a receiver closer to the driver — which sounds like moving it out of harm’s way — makes its interval longer.

Half the swing is not a level. On a 3.3-volt logic family it is 1.65 volts, which is above every input low threshold and below every input high threshold in use, so the receiver’s output during that interval is whatever its own internal gain and noise decide. If the receiver is a clocked one and the clock arrives in that window, the bit is a coin toss. If it is a latch, it can double-clock.

A series-terminated net holds half a swing for 1.5 delays at 25% along it. computed by solving, not by drawing. What a receiver 25% of the way along one net sees under three terminations, from a lattice evaluated at that point rather than at the ends. The shaded strip is the interval in which a logic input has no defined answer — between 30% and 70% of the swing. The series-terminated net sits in it for 7.25 ns, which is 2(1 − x) delays exactly and is zero only at the far end; the unterminated net sits in it for 2.42 ns and then overshoots by 82%; the parallel-terminated net never does, and draws 60 mA down the line for as long as the level is held.
Fig. 2 A quarter of the way along, where the interval is a delay and a half — longer, because the reflected wave has further to come back. The nearer to the source a receiver stands, the worse the series scheme treats it.
A series-terminated net holds half a swing for 0.0 delays at 100% along it. computed by solving, not by drawing. What a receiver 100% of the way along one net sees under three terminations, from a lattice evaluated at that point rather than at the ends. The shaded strip is the interval in which a logic input has no defined answer — between 30% and 70% of the swing. The series-terminated net sits in it for 0.00 ns, which is 2(1 − x) delays exactly and is zero only at the far end; the unterminated net sits in it for 9.68 ns and then overshoots by 82%; the parallel-terminated net never does, and draws 60 mA down the line for as long as the level is held.
Fig. 3 And at the far end, where the two arrivals coincide and the interval is exactly zero. This is the picture every account of series termination draws, and it is a picture of one point on the net.

The unterminated net is the mirror image

The scheme with no resistor in it at all has an interval of its own, and it is worth measuring because its shape is the opposite.

Its first wave is nearly the whole swing rather than half of it, so an interior receiver is not stuck at an ambiguous level after the first arrival — it is stuck near the top. What it is stuck at before the first arrival is zero, which is a perfectly good level, so the ambiguity has to be looked for elsewhere: it is in the overshoot and ringing after the far end doubles the wave and the low impedance source sends it back inverted.

Measured with the same criterion — the longest interval spent between thirty and seventy per cent of the final value, after the first arrival — the unterminated net gives 2x2x delays. Zero-point-two at a tenth of the way along, 1.00 at halfway, 2.00 at the far end.

So the two schemes are worst at opposite ends of the net. The series resistor is perfect at the far end and worst near the source; no termination at all is best near the source and worst at the far end. A designer who has both receivers on one net has no good answer from either.

A 1 V step onto 1.00 m of 50 Ω line into an open circuit. computed by solving, not by drawing as a sum of 81 arrivals. The source drives 0.8333 V into the line immediately — set by 10 Ω against the line's 50 Ω, and not by the load, which it cannot yet know about. One delay of 4.83 ns later the far end reaches 1.6666 V. The staircase settles at 0.999990 V, which is what the resistive divider gives.
Fig. 4 The staircase read at the ends, from earlier in this field, where the source’s reflection coefficient and the load’s produce a converging series whose limit is the resistive divider it must converge to.
20 inductor-capacitor sections, against the line they are meant to be. computed by solving, not by drawing by the trapezoidal rule over 2,600 steps. The LC ladder reaches two per cent of full scale at 0.86 delays, before the wave picture says anything can have arrived, and its plateaus are wrong by up to 0.079 V. Neither is a small correction to the wave answer; they are what a network of 20 poles does when asked to be a delay.
Fig. 5 And the same step computed by a lumped ladder that has never heard of a wave, which reproduces the staircase and shows what a finite number of sections costs.

What the parallel resistor costs, exactly

The third scheme has no interval anywhere, at any position, under any criterion, because nothing reflects: the wave that arrives is the final value and there is no second arrival to wait for.

What it costs is a current. With a 3.3-volt swing into a fifty-ohm termination and a five-ohm driver, sixty milliamperes flows down the line for as long as the level is held — 198 milliwatts, per net, at whatever fraction of the time the net is at that level.

Against that, the series scheme’s static current is the receiver’s input leakage: 3.3 nanoamperes in this model, and in practice a few microamperes. Seven orders of magnitude.

That is the whole trade and it is not subtle. A parallel termination is right everywhere on the net and costs continuous power; a series termination costs nothing and is right at one point on the net. Which one a design uses is decided by how many receivers there are and where they are, and the arithmetic above is what “where they are” means.

A series-terminated net holds half a swing for 1.8 delays at 10% along it. computed by solving, not by drawing. What a receiver 10% of the way along one net sees under three terminations, from a lattice evaluated at that point rather than at the ends. The shaded strip is the interval in which a logic input has no defined answer — between 30% and 70% of the swing. The series-terminated net sits in it for 8.69 ns, which is 2(1 − x) delays exactly and is zero only at the far end; the unterminated net sits in it for 0.97 ns and then overshoots by 82%; the parallel-terminated net never does, and draws 60 mA down the line for as long as the level is held.
Fig. 6 The receiver a tenth of the way along. The series-terminated line has no defined level at the receiver for 1.80 delays, while the parallel-terminated one has none at all — and the parallel resistor is drawing 60 mA the whole time. What the parallel resistor costs, exactly, is that current, and it costs it continuously rather than during the transition.
A series-terminated net holds half a swing for 0.5 delays at 75% along it. computed by solving, not by drawing. What a receiver 75% of the way along one net sees under three terminations, from a lattice evaluated at that point rather than at the ends. The shaded strip is the interval in which a logic input has no defined answer — between 30% and 70% of the swing. The series-terminated net sits in it for 2.43 ns, which is 2(1 − x) delays exactly and is zero only at the far end; the unterminated net sits in it for 7.25 ns and then overshoots by 82%; the parallel-terminated net never does, and draws 60 mA down the line for as long as the level is held.
Fig. 7 Three quarters along: the undefined stretch falls to 0.50 delays. Series termination is a plateau problem and parallel termination is a power problem, and neither is a matter of taste — the receiver’s position decides how long the first lasts, and nothing decides the second.

Where the half-amplitude wave comes from

It is worth being explicit about the half, because it is deliberate and it is what makes the interior interval exist at all.

The wave a source launches onto a line is set by a divider between the source impedance and the characteristic impedance — not the load, which the source has no way of knowing about for another two delays. That is the surprise this field opens with, and it is why a series termination works: make the source impedance equal to the characteristic impedance and the divider is exactly one half.

The far end then doubles it. An open end has a reflection coefficient of one, so the incident wave and its reflection add, and the receiver at the end sees the full swing. The reflection travels back, arrives at a source that now matches the line, and is absorbed with nothing left over.

So the scheme’s whole correctness rests on an arrangement that is only complete after the round trip, and the half-amplitude interval is not a defect in it — it is the intermediate state of a mechanism that has to have one. Measured here: the launched wave is 1.650 volts of a 3.300-volt swing, which is a half to four figures, and the source’s reflection coefficient is zero to the arithmetic.

That is also why the trick cannot be repaired by choosing a different resistor. Making the launched wave larger would leave the source mismatched and the returning wave would reflect; making it smaller would leave the receiver short of the full swing. The half is forced.

A series-terminated net holds half a swing for 0.2 delays at 90% along it. computed by solving, not by drawing. What a receiver 90% of the way along one net sees under three terminations, from a lattice evaluated at that point rather than at the ends. The shaded strip is the interval in which a logic input has no defined answer — between 30% and 70% of the swing. The series-terminated net sits in it for 0.97 ns, which is 2(1 − x) delays exactly and is zero only at the far end; the unterminated net sits in it for 8.70 ns and then overshoots by 82%; the parallel-terminated net never does, and draws 60 mA down the line for as long as the level is held.
Fig. 8 Nine tenths: 0.20 delays. Across the positions drawn — 10%, 25%, 50%, 75% and 90% — the undefined stretch runs 1.80, 1.50, 1.00, 0.50 and 0.20 delays, which is 2(1−x) exactly. Where the half-amplitude wave comes from is the source resistor matching the line: the driver launches half its voltage, and the receiver sees nothing else until the far-end reflection arrives.

What a real measurement of this looks like

Two practical remarks, because the interval this essay measures is one that a bench measurement finds easily and a simulation can miss.

An oscilloscope probe is an interior receiver, so probing a series-terminated net anywhere but at its far end shows the half-amplitude step directly — and the usual reaction is that the probe or the driver is faulty. It is neither; the plateau is real, it is what the receiver at that point sees, and the far end is fine.

And the interval scales with the line rather than with the driver. Doubling the length doubles both arrivals and doubles the plateau, so a net that works at one length fails at two with nothing about the signal changed — which is the same substitution hazard as a faster driver, arriving from the other direction.

The condition under which none of this matters

Everything above assumes the line is a line. If the round trip is short compared with the edge, the reflections all arrive during the transition and there is no plateau to sit on: the waveform is a somewhat slowed edge and nothing more.

That is the lumped-element boundary this collection computes, and it is the reason a great deal of digital wiring needs no termination at all. The usual rule of thumb is that a net is electrically short if its round-trip delay is less than the edge’s rise time; on a metre of the line here the round trip is 9.67 nanoseconds, so a signal with a one-nanosecond edge needs all of this and a signal with a twenty-nanosecond edge needs none of it.

The rule is worth stating in the form the boundary gives it, which is about the length rather than about the frequency: the same net is a lumped capacitance for a slow driver and a transmission line for a fast one, and replacing the driver with a faster part — which is the sort of thing a supply-chain substitution does — moves the net across the boundary without anything in the schematic changing.

Two arrangements this essay does not measure

Both are common and both need machinery beyond the three-element lattice above.

Termination at both ends — a series resistor at the source and a parallel one at the load — removes the interior interval and halves the received amplitude, since the launched half-swing is no longer doubled by anything. It is used where the receiver has margin to spare and the net has stubs. The lattice handles it, but the received level is then a divider question rather than a reflection question and belongs with the essay about what a driver actually drives.

A stub, which is what an interior receiver usually is in practice: not a point on the line but a short branch off it, with its own delay and its own open end. A stub reflects, and whether it matters is decided by its round trip against the edge — the same boundary as above, applied to a much shorter length. This is the arrangement that makes a mid-net receiver tolerable in practice, and computing it needs a lattice with a junction in it, which this one does not have.

Naming them is not a substitute for measuring them. What can be said from here is that both are ways of attacking the same quantity this essay measures — the interval during which an interior receiver has no answer — and that neither removes it for nothing.

What the termination decision costs

Series and parallel termination fail differently, and three other essays in the field price the difference. The receiver that is a branch is the same decision with a stub, where the undefined stretch acquires a plateau of its own. Where the current comes back is where the characteristic impedance both terminations are matched to comes from. The staircase in time is the wave picture underneath, and A ladder is not a line is what a lumped model of it would be worth.

What is checked

Four assertions, and the first is an expression rather than a number.

That a series-terminated net holds half the swing at an interior receiver for 2(1−x)2(1-x) delays, to two per cent, at every position the slider offers — an expression in the position, checked at eight of them, rather than a value at one.

That a parallel-terminated net has no such interval anywhere, exactly zero, because nothing reflects and the wave is right when it arrives.

That what that costs is a current down the line — sixty milliamperes against the series scheme’s nanoamperes — so that the comparison carries its price beside its benefit.

And that the unterminated net’s own interval is 2x2x, the mirror image, which is what makes the choice a question about where the receivers are rather than a question about which scheme is better.

Where the receivers actually are

The interval 2(1−x)2(1-x) is a statement about a receiver at a fraction xx along the net, and a real net does not have its receivers on it — they hang off it. The receiver that is a branch is the correction, and it changes the arithmetic rather than adding to it: an interior receiver is a short piece of track leading off the net to a pin, open at the far end, and three lines of equal impedance meeting at a junction present each other with half the impedance. So a wave arriving is reflected by exactly minus a third and two thirds goes on, the far end of the stub receives two thirds of the swing and sits there for twice the stub’s own delay — whatever the net is terminated with and wherever on it the branch is.

That is a different kind of statement from this essay’s. The half-swing interval measured here belongs to the termination scheme and can be designed away by putting the receivers at the far end; the two-thirds interval belongs to the branch and cannot, because it is set by the impedance three conductors present to each other and by the stub’s length. A designer who has read this essay and moved every receiver to the end of the net has removed the first and kept the second, and the second is the one that scales with how the parts are placed rather than with the scheme.

The two together give the practical rule the field is for: choose the termination for where the receivers are, and choose the stub lengths for how long the level has to be right. The first is a schematic decision and the second is not — which puts it with the edges that are lengths, among the boundaries set by whoever builds the thing.

Sixty milliamperes, and what it is being compared with

The parallel-terminated scheme’s cost is stated here as a current — sixty milliamperes for as long as the level is held, against the series scheme’s nanoamperes — and that number deserves a second look, because a static current in a digital circuit is not merely a power figure.

It is a current drawn from a supply that is not a supply at every frequency. A source below a frequency measures a regulator’s output impedance at 0.43 milliohms at direct current and 1.95 ohms at ten kilohertz, and the pair that is worse than either finds the decoupling network presenting six times the impedance either capacitor does alone at the frequency between them. Sixty milliamperes switching on and off at a clock rate is therefore a current step into a rising impedance, and what it produces is a voltage on the rail shared by everything else on the board — which the millivolts in the wire shows arriving in a ten-millivolt measurement as five per cent of it before anything has been amplified.

So the comparison between the two schemes is not sixty milliamperes of power against a shorter interval of ambiguity. It is a static current whose consequences appear somewhere else on the board against a timing artefact whose consequences appear on this net. Both are real, they are charged to different budgets, and the reason the series scheme is the common choice on dense boards is the first of them rather than anything on this page.

Which is worth stating as a caution about how this essay reads. Everything measured here is on one net, and the argument between the two schemes is settled on one net only if nothing else shares anything with it. Sixty milliamperes per net, on a bus of thirty-two, is a supply-current step somebody has to decouple — and the decoupling network that does it is the one the pair that is worse than either shows presenting six times the impedance either capacitor does alone at the frequency between them.

Part 1 on termination

One argument about Termination, and one of 3 essays on it so far, each part numbered by how much of the idea it assumes. What sits either side of it:

A stub holds the far end at two thirds for twice its own delay. computed by solving, not by drawing. A series-terminated net with a branch on it, marched as waves on a delay grid. Three lines of equal impedance meet at the junction, so each presents the others with Z₀/2 and a wave arriving is reflected by exactly −1/3 with two thirds going on. The far end therefore receives 66.7% of the swing at one line delay instead of all of it, and is held there for 0.400 line delays — twice the stub's own delay of 0.41 ns, being the round trip to its open end and back. The same net without the branch is drawn beside it and settles in one round trip, which is what a series termination is for. Each further round trip of the stub divides what is left of the error by three and turns it over, because the returning wave doubles at the open far end — so the receiver approaches its level alternately from below and from above. The receiver that is a branch Part 2 — A lattice diagram has two ends, and an interior receiver is not a point on a net — it is a short piece of track leading off it to a pin, open at the far end. Three lines of equal impedance meeting at a junction present each other with half the impedance, so a wave arriving is reflected by exactly minus a third and two thirds goes on: the far end receives two thirds of the swing and sits there for twice the stub's own delay, whatever the net is terminated with and wherever on it the branch is.

Where this goes next

A 1 V step onto 1.00 m of 50 Ω line into an open circuit. computed by solving, not by drawing as a sum of 81 arrivals. The source drives 0.8333 V into the line immediately — set by 10 Ω against the line's 50 Ω, and not by the load, which it cannot yet know about. One delay of 4.83 ns later the far end reaches 1.6666 V. The staircase settles at 0.999990 V, which is what the resistive divider gives. The staircase in time A source driving a metre of cable does not know what is on the far end of it for 4.83 nanoseconds. What it drives into during that time is decided by the cable's characteristic impedance and nothing else — and when the far end finally answers, the answer comes back as a staircase whose limit is the resistive divider the circuit was going to be all along. 20 inductor-capacitor sections, against the line they are meant to be. computed by solving, not by drawing by the trapezoidal rule over 2,600 steps. The LC ladder reaches two per cent of full scale at 0.86 delays, before the wave picture says anything can have arrived, and its plateaus are wrong by up to 0.079 V. Neither is a small correction to the wave answer; they are what a network of 20 poles does when asked to be a delay. A ladder is not a line A transmission line is usually introduced as the limit of a chain of inductors and capacitors as the number of sections goes to infinity. That is true, and it gives entirely the wrong impression of how close a finite chain gets. Forty sections still ring through every plateau by five per cent, and extrapolating the fitted convergence, reaching one per cent would need about nine hundred and sixty. The return under 10.0 cm of track, 200 µm above the plane. computed by solving, not by drawing, as an estimate from the geometry: a low-frequency path assumed to be three track-widths wide, 83.3 mΩ, and the parallel-plate inductance µ₀h/w, 125.7 nH, which is the limit for a track much wider than its height. The estimated resistance and reactance are equal at 106 kHz. Solved across the plane instead of assumed, the return does not change path at one frequency: it gathers beneath the track across a band about three decades wide, and this corner falls inside that band. Above the band the loop is the track's length times its height, 20.0 mm², and a milliamp round it at 100 MHz radiates -1.1 dBµV/m at three metres. Where the current comes back The return current under a track spreads out at low frequency and runs directly beneath it at high. Estimated from two paths chosen in advance, the change is a corner at 106 kilohertz for any track two hundred micrometres above a half-milliohm plane, with neither the length of the track nor its width in it. Solved, it is a band three decades wide rather than a corner, and the width enters it after all — but the length is still absent and the stack-up still sets the top, which is the part of the argument a designer needs.

What links here

Essays that reach for this one mid-argument — the half of a link its own author cannot write down.

What this makes readable

Essays that name this one as a prerequisite.

The objects named here

The third axis, after the field and the idea: the things themselves, and every essay that touches each one.

Design tradeoffLattice diagramLogic thresholdPropagation delayReflection coefficientTermination