The staircase in time

Kirchhoff’s own frequency computes where the lumped model of a piece of copper gives out — 3.97 MHz for ten centimetres of track, if one degree of phase error is the threshold — and stops there, because everything past that point needs a different object. This is that object.

A transmission line is not a component with a value. It is a delay with a characteristic impedance, and the two facts that follow from that description are the whole of the field: a signal arrives late, and what it does on arrival depends on what it finds there.

What the source drives into #

The first value on the staircase is the one worth pausing on, because it is not the one a lumped picture predicts.

A ten-ohm source driving an open circuit through a wire should produce a volt. It produces 0.833 V, and it does so for 9.67 nanoseconds, because for that time the source is not driving an open circuit — it is driving a line, and a line looks like a resistance of fifty ohms to anything that has not yet had time to hear back from the other end.

That resistance is the characteristic impedance, and it is not a resistor. Nothing dissipates. What is happening is that the source is pouring energy into the electric and magnetic fields of the cable at a fixed ratio of voltage to current, and that ratio is √(L′/C′) — the inductance per metre over the capacitance per metre, both of which are properties of the cable’s geometry and its dielectric.

So the launched wave is set by a divider between the source resistance and a number that has nothing to do with the load: 1 V × 50/(10 + 50) = 0.833 V. The load’s influence arrives one propagation delay later, and this figure’s first assertion is precisely that: the far end sits at zero to fifteen decimal places until the delay has elapsed.

The staircase, and where it is heading #

What comes back is decided by the reflection coefficient, $\Gamma = (Z_L - Z_0)/(Z_L + Z_0)$, and the three cases worth naming all appear on the slider.

An open circuit has Γ = +1: the whole wave comes back with the same sign, the far end doubles to 1.667 V, and the near end goes to 1.111 V one delay later. A short circuit has Γ = −1 and everything cancels. A matched load at fifty ohms has Γ = 0, the wave is absorbed, and the staircase has exactly one step — which is why matched terminations exist.

Everything else is between. A hundred ohms gives Γ = 0.333 and a far end of 1.111 V; twelve and a half ohms gives Γ = −0.6 and a far end of 0.333 V.

The reflections then bounce between the two ends, each round trip multiplying by $\Gamma_s\Gamma_L$, and since both ends are passive the product is less than one in magnitude and the series converges. Where it converges to is the check.

Two routes, and one of them has no waves in it #

Summing the geometric series gives $v_1(1 + \Gamma_L)/(1 - \Gamma_s\Gamma_L)$. That is a statement about waves, delays and reflections.

Solving the circuit as a resistive divider gives $V_s R_L/(R_s + R_L)$. That is a statement about a settled circuit with no time in it at all, and it does not know that a cable is present.

They agree to a part in 10⁹ at every load on the slider. For the open-circuit case both give 0.99999; for a hundred ohms both give 0.90909; for twelve and a half ohms both give 0.55556.

That agreement is not a coincidence and it is not trivial either. It says that all the structure in the middle of the picture — the delay, the doubling, the overshoot to 1.667 V, the ringing down — is transient, and that what the circuit settles to was decided before any of it happened. The cable changes when the answer arrives and by what route; it does not change the answer.

Three ways to stop it, and what each costs #

Termination is the practical answer, and there are three arrangements in common use. All of them make Γ zero somewhere; they differ in where, and in what they cost.

Parallel termination puts a resistor equal to the characteristic impedance at the far end, so $\Gamma_L = 0$ and nothing reflects. The staircase becomes a single step. What it costs is direct current: the resistor is across the line permanently, so a driver holding a logic high into fifty ohms delivers current for as long as it holds it, and a 3.3 V signal into a fifty-ohm termination draws 66 mA continuously. For a bus with many signals that is the dominant power consumption of the interface.

Series termination puts a resistor at the source instead, chosen so the source resistance plus the resistor equals the characteristic impedance. $\Gamma_s$ is then zero. The far end still reflects — it is usually a high-impedance input, so $\Gamma_L$ is very nearly +1 — but the reflection returns to a matched source and is absorbed there. The far end sees one step, of full amplitude, arriving one delay late; the near end sees a half-amplitude step for one round trip and then the full value. It costs no direct current at all, which is why it is used almost universally for point-to-point signals, and it fails the moment there is more than one receiver, because anything tapped part-way along the line sees the half-amplitude plateau.

Alternating-current termination puts a resistor and a capacitor in series at the far end, so the line is terminated at the frequencies where the edge lives and open at direct current. It buys the single-step response of parallel termination without the standing current, and it costs a component and a time constant that has to be chosen against the signal’s own timing.

The choice among the three is a good example of what this collection means by a model with an edge: each is exactly right under conditions that can be stated, and each fails in a specific, computable way when the conditions do not hold.

Why the overshoot matters more than the delay #

A delay is inconvenient. An overshoot to twice the driven voltage is a fault.

The far end of an unterminated line reaches 1.667 V from a one-volt source in this example, and with a source resistance smaller than ten ohms it gets closer to 2 V. Digital logic driven that way sees its input exceed the supply rail, which forward-biases the protection diodes; and on the way down after the next reflection it sees the input pass back through the switching threshold, which is a second edge the receiver was not sent.

That second edge is the practical content of this whole field. A signal that crosses its threshold three times when it was supposed to cross once produces three clock edges, and no amount of care in the logic design prevents it, because the fault is in the copper.

How long the line has to be #

The condition for any of this to matter is not the length of the cable but the length of the cable compared with the edge.

A signal whose rise time is long compared with the round-trip delay never sees a staircase: the reflections come back and add while the edge is still rising, and the result is a slightly rounded edge with no structure in it. The staircase appears when the rise time is short compared with $2T_d$, and the usual rule of thumb puts the boundary at a rise time of about twice the round-trip delay.

For the metre of line drawn here, $T_d$ is 4.83 ns and the round trip is 9.67 ns, so a signal with a rise time under about twenty nanoseconds will show the structure. That is not a demanding requirement — it is comfortably slower than any logic family in use — which is why termination is a routine part of board design rather than a specialist concern.

The scaling is worth stating because it is linear and unforgiving. A ten-centimetre track has a round trip of about a nanosecond, so an edge faster than two nanoseconds sees it. A one-centimetre track sees edges faster than two hundred picoseconds. Every generation of faster logic moves the boundary down by the same factor it moves the edge, and the length of copper that counts as “short” shrinks with it.

What the wave picture is worth #

That last figure is the argument of a ladder is not a line, and its conclusion is stronger than “the lumped model is an approximation”.

A transmission line is often introduced as the limit of a ladder of inductors and capacitors as the number of sections goes to infinity. That is true, and it gives entirely the wrong impression of how close a finite ladder gets. Forty sections still ring through every plateau, still smear the edge over a tenth of a delay, and — extrapolating the measured convergence — reaching one per cent on the plateaus would need something close to a thousand sections.

So the staircase is not a shortcut. It is the right description, and the lumped picture is the approximation — which is the opposite of the order they are usually taught in, and the reason this field exists as something other than an appendix to the limits field.

Where the characteristic impedance comes from #

One number in this essay has been used without being derived, and it is the one everything else hangs on.

The characteristic impedance is √(L′/C′), and both of those are properties of the cable’s cross section. For a coaxial cable the inductance per metre is (μ₀/2π)ln(b/a) and the capacitance per metre is 2πε/ln(b/a), with a and b the inner and outer radii, so the ratio depends on the geometry only through that logarithm and the impedance is (1/2π)√(μ/ε) ln(b/a). Everything about the size of the cable cancels except the ratio of the two radii.

That is why fifty ohms is a number rather than a range. It corresponds to a particular ratio of radii in a particular dielectric, and a cable of that impedance can be made a millimetre across or a hand across. It is also why the propagation velocity is c/√ε_r and depends on nothing else at all: the product L′C′ works out to με regardless of the geometry, so the delay per metre is set by the dielectric alone.

The library derives the two per-metre quantities from the impedance and the dielectric rather than the other way round — L′ = Z₀/v and C′ = 1/(Z₀v) — because those are the two numbers a datasheet gives. That inversion is what keeps the two routes in this field genuinely separate: the lattice uses the impedance and the delay, the ladder uses the inductance and capacitance, and the only thing they share is the line’s specification.

What is not here #

Three things are absent from this page and are worth naming rather than leaving to be noticed.

Loss. Every line drawn here is lossless, so the staircase’s steps are decided entirely by the reflection coefficients. A real cable attenuates, so each round trip is smaller than the geometric series says, and the staircase converges faster than it should. The next essay in this field puts attenuation into the line model for the one claim that needs it — a quarter-wave short circuit is an open circuit only if nothing dissipates — and leaves it out elsewhere.

Dispersion. The velocity here is c/√ε_r, a constant. In a real dielectric it varies with frequency, so the components of an edge travel at different speeds and the edge spreads as it goes. Over a metre this is negligible; over a hundred metres it is the dominant effect.

Anything other than a step. The lattice sums step arrivals. A general waveform is a superposition of steps and could be handled the same way, and is not, because the step is where the argument is.

One more thing the two routes agree about #

There is a second, quieter check available in the staircase and it is worth reading out, because it tests something the divider comparison does not.

The divider comparison tests the limit. It says nothing about the individual steps, and a lattice with a sign error in one of its two reflection coefficients could easily converge to the right place by a wrong route. So the figure also asserts what the far end is doing before the first arrival: at 0.999 of a propagation delay it is at zero, and the assertion is to fifteen decimal places rather than to a tolerance.

Together the two say something quite specific. The staircase gets to the right answer, and it gets there without anything happening before it could have. A model that had the delay wrong would fail the second; one that had the reflections wrong would fail the first; and a model that had both wrong in compensating ways would have to be wrong in a way that is hard to arrive at by accident.

That is the shape this collection reaches for whenever it can. Two checks that fail on different mistakes are worth much more than two checks that fail on the same one, and the pair here is unusually well separated: one is about a limit computed with no time in it, and the other is about what happens in the first five nanoseconds.

What the staircase does to the two things standing on either side of it #

The interval before the far end answers is 4.83 nanoseconds for a metre, and what matters about it is not its length but that during it the source is driving a resistance it did not choose and cannot see on the schematic.

Looking back towards the source, that is a load an amplifier meets and does not expect. The resistor that buys the margin back treats a metre of cable as 905 picofarads — which it is, at frequencies where the whole cable is short compared with a wavelength — and notes in the same breath that ten metres is not a capacitance at all by the frequency the loop cares about. Between those two the load an amplifier sees is neither a capacitance nor a resistance but a resistance for a round trip and then whatever the far end makes of it, which is a load no phase margin describes.

Looking forward, the staircase is what a logic input is asked to interpret. The resistor at the wrong end is where that becomes a design question: the two respectable terminations look identical at the two ends of the line and differ entirely in the middle, where a series-terminated net holds half its swing for a full round trip — an interval of $2(1-x)$ delays, zero only at the far end. Every step of the staircase drawn here is one of those intervals seen from the source’s end.

And a ladder is not a line is the reminder that the object drawn here is a chain rather than a line: forty sections still ring through every plateau by five per cent, so the flatness of the treads is the model’s rather than the cable’s, and the heights are the ones to read.

And the treads are not flat on a real cable either, for a different reason. The delay that is not one number finds a trace’s series resistance turning the line into a diffusion below 910 kilohertz for ordinary copper, with the rise time growing as the square of the length while the arrival stays exactly linear in it. So the staircase’s timing — which is what a lattice diagram is for — survives the correction intact, and the sharpness of each step does not: over a long enough run the edges soften until consecutive treads merge, and the picture stops being a staircase before the arithmetic behind it stops being right.

What the staircase is used for #

A wave picture checked against a resistive divider is what the rest of this field is built on. The resistor at the wrong end is the termination decision it makes possible. The receiver that is a branch is the same lattice with a third node. A ladder is not a line is the lumped approximation measured against it, converging as N to the −0.54 power, and One step, computed twice is the transients field’s own two-route habit that this one is an instance of.