Lines, where a wire has a length

The staircase in time

A source driving a metre of cable does not know what is on the far end of it for 4.83 nanoseconds. What it drives into during that time is decided by the cable's characteristic impedance and nothing else — and when the far end finally answers, the answer comes back as a staircase whose limit is the resistive divider the circuit was going to be all along.

Kirchhoff’s own frequency computes where the lumped model of a piece of copper gives out — 3.97 MHz for ten centimetres of track, if one degree of phase error is the threshold — and stops there, because everything past that point needs a different object. This is that object.

A transmission line is not a component with a value. It is a delay with a characteristic impedance, and the two facts that follow from that description are the whole of the field: a signal arrives late, and what it does on arrival depends on what it finds there.

A 1 V step onto 1.00 m of 50 Ω line into an open circuitcomputed by solving, not by drawing as a sum of 81 arrivals. The source drives 0.8333 V into the line immediately — set by 10 Ω against the line's 50 Ω, and not by the load, which it cannot yet know about. One delay of 4.83 ns later the far end reaches 1.6666 V. The staircase settles at 0.999990 V, which is what the resistive divider gives.00.50011.5002468time, in propagation delaysvoltsthe divider: 1.0000 V0.833 V: the source against the linethe far endthe near endfirst arrival, 4.83 nssolved, then checked — a series against a dividernothing at the far end before 4.83 ns
Fig. 1 A one-volt step onto a metre of fifty-ohm line with an open circuit at the far end, seen at both ends. The near end goes first, to 0.833 V, a value the load has no part in. One delay of 4.83 ns later the far end reaches 1.667 V — twice the incident wave, because an open circuit reflects everything — and one delay after that the near end finds out. The slider is the load resistance, and the dashed line is where the staircase must end up.

What the source drives into

The first value on the staircase is the one worth pausing on, because it is not the one a lumped picture predicts.

A ten-ohm source driving an open circuit through a wire should produce a volt. It produces 0.833 V, and it does so for 9.67 nanoseconds, because for that time the source is not driving an open circuit — it is driving a line, and a line looks like a resistance of fifty ohms to anything that has not yet had time to hear back from the other end.

That resistance is the characteristic impedance, and it is not a resistor. Nothing dissipates. What is happening is that the source is pouring energy into the electric and magnetic fields of the cable at a fixed ratio of voltage to current, and that ratio is √(L′/C′) — the inductance per metre over the capacitance per metre, both of which are properties of the cable’s geometry and its dielectric.

So the launched wave is set by a divider between the source resistance and a number that has nothing to do with the load: 1 V × 50/(10 + 50) = 0.833 V. The load’s influence arrives one propagation delay later, and this figure’s first assertion is precisely that: the far end sits at zero to fifteen decimal places until the delay has elapsed.

The staircase, and where it is heading

What comes back is decided by the reflection coefficient, Γ = (Z_L − Z₀)/(Z_L + Z₀), and the three cases worth naming all appear on the slider.

An open circuit has Γ = +1: the whole wave comes back with the same sign, the far end doubles to 1.667 V, and the near end goes to 1.111 V one delay later. A short circuit has Γ = −1 and everything cancels. A matched load at fifty ohms has Γ = 0, the wave is absorbed, and the staircase has exactly one step — which is why matched terminations exist.

Everything else is between. A hundred ohms gives Γ = 0.333 and a far end of 1.111 V; twelve and a half ohms gives Γ = −0.6 and a far end of 0.333 V.

The reflections then bounce between the two ends, each round trip multiplying by Γ_s Γ_L, and since both ends are passive the product is less than one in magnitude and the series converges. Where it converges to is the check.

Two routes, and one of them has no waves in it

Summing the geometric series gives v₁(1 + Γ_L)/(1 − Γ_s Γ_L). That is a statement about waves, delays and reflections.

Solving the circuit as a resistive divider gives V_s R_L/(R_s + R_L). That is a statement about a settled circuit with no time in it at all, and it does not know that a cable is present.

They agree to a part in 10⁹ at every load on the slider. For the open-circuit case both give 0.99999; for a hundred ohms both give 0.90909; for twelve and a half ohms both give 0.55556.

That agreement is not a coincidence and it is not trivial either. It says that all the structure in the middle of the picture — the delay, the doubling, the overshoot to 1.667 V, the ringing down — is transient, and that what the circuit settles to was decided before any of it happened. The cable changes when the answer arrives and by what route; it does not change the answer.

A 1 V step onto 1.00 m of 50 Ω line into 12.5 Ωcomputed by solving, not by drawing as a sum of 81 arrivals. The source drives 0.8333 V into the line immediately — set by 10 Ω against the line's 50 Ω, and not by the load, which it cannot yet know about. One delay of 4.83 ns later the far end reaches 0.3333 V. The staircase settles at 0.555556 V, which is what the resistive divider gives.00.2500.5000.750102468time, in propagation delaysvoltsthe divider: 0.5556 V0.833 V: the source against the linethe far endthe near endfirst arrival, 4.83 nssolved, then checked — a series against a dividernothing at the far end before 4.83 ns
Fig. 2 The same step into twelve and a half ohms, a quarter of the line’s impedance. The reflection coefficient is −0.6, so the far end undershoots: it goes to 0.333 V rather than the 0.556 V it will settle at, and climbs from below. An open circuit overshoots and a short undershoots; the sign of Γ decides which, and it changes at the characteristic impedance.

Three ways to stop it, and what each costs

Termination is the practical answer, and there are three arrangements in common use. All of them make Γ zero somewhere; they differ in where, and in what they cost.

Parallel termination puts a resistor equal to the characteristic impedance at the far end, so Γ_L = 0 and nothing reflects. The staircase becomes a single step. What it costs is direct current: the resistor is across the line permanently, so a driver holding a logic high into fifty ohms delivers current for as long as it holds it, and a 3.3 V signal into a fifty-ohm termination draws 66 mA continuously. For a bus with many signals that is the dominant power consumption of the interface.

Series termination puts a resistor at the source instead, chosen so the source resistance plus the resistor equals the characteristic impedance. Γ_s is then zero. The far end still reflects — it is usually a high-impedance input, so Γ_L is very nearly +1 — but the reflection returns to a matched source and is absorbed there. The far end sees one step, of full amplitude, arriving one delay late; the near end sees a half-amplitude step for one round trip and then the full value. It costs no direct current at all, which is why it is used almost universally for point-to-point signals, and it fails the moment there is more than one receiver, because anything tapped part-way along the line sees the half-amplitude plateau.

Alternating-current termination puts a resistor and a capacitor in series at the far end, so the line is terminated at the frequencies where the edge lives and open at direct current. It buys the single-step response of parallel termination without the standing current, and it costs a component and a time constant that has to be chosen against the signal’s own timing.

The choice among the three is a good example of what this collection means by a model with an edge: each is exactly right under conditions that can be stated, and each fails in a specific, computable way when the conditions do not hold.

Why the overshoot matters more than the delay

A delay is inconvenient. An overshoot to twice the driven voltage is a fault.

The far end of an unterminated line reaches 1.667 V from a one-volt source in this example, and with a source resistance smaller than ten ohms it gets closer to 2 V. Digital logic driven that way sees its input exceed the supply rail, which forward-biases the protection diodes; and on the way down after the next reflection it sees the input pass back through the switching threshold, which is a second edge the receiver was not sent.

That second edge is the practical content of this whole field. A signal that crosses its threshold three times when it was supposed to cross once produces three clock edges, and no amount of care in the logic design prevents it, because the fault is in the copper.

10.0 cm of track, solved as a lumped circuit and as a lineThe two agree to 0.030% at 3.97 MHz, where the track is one degree long, and to 30.1% at 143 MHz, where it is a tenth of a wavelength. Above that the lumped model is not approximately right; it is describing a different object.1101001k10k100k1M10M100M1Gfrequency (hertz)impedance looking into 10.0 cm of track (ohms)the lumped model: one L, one C1° long at 3.97 MHza tenth of a wavelength at 143 MHzthe 200 Ω at the far endsolved, then checked — the line against a two-element modelKirchhoff's laws run out at 143 MHz
Fig. 3 The same piece of track solved as a lumped inductance and capacitance and as a transmission line, from the limits field. Below the crossover the two lie on top of each other; above it the lumped model has no vocabulary for what the line does. The staircase on this page lives entirely on the right-hand side of that crossover.

How long the line has to be

The condition for any of this to matter is not the length of the cable but the length of the cable compared with the edge.

A signal whose rise time is long compared with the round-trip delay never sees a staircase: the reflections come back and add while the edge is still rising, and the result is a slightly rounded edge with no structure in it. The staircase appears when the rise time is short compared with 2T_d, and the usual rule of thumb puts the boundary at a rise time of about twice the round-trip delay.

For the metre of line drawn here, T_d is 4.83 ns and the round trip is 9.67 ns, so a signal with a rise time under about twenty nanoseconds will show the structure. That is not a demanding requirement — it is comfortably slower than any logic family in use — which is why termination is a routine part of board design rather than a specialist concern.

The scaling is worth stating because it is linear and unforgiving. A ten-centimetre track has a round trip of about a nanosecond, so an edge faster than two nanoseconds sees it. A one-centimetre track sees edges faster than two hundred picoseconds. Every generation of faster logic moves the boundary down by the same factor it moves the edge, and the length of copper that counts as “short” shrinks with it.

20 inductor-capacitor sections, against the line they are meant to becomputed by solving, not by drawing by the trapezoidal rule over 2,600 steps. The ladder reaches two per cent of full scale at 0.86 delays, before the wave picture says anything can have arrived, and its plateaus are wrong by up to 0.079 V. Neither is a small correction to the wave answer; they are what a network of 20 poles does when asked to be a delay.00.50011.50202468time, in propagation delaysvolts at the far endthe wave answer20 sectionsone delaysolved, then checked — a ladder against a latticeplateaus 0.08 V out at 20 sections
Fig. 4 The same step computed by a chain of twenty inductor-capacitor sections, marched forward in time by the trapezoidal rule. The ladder knows nothing about waves, delays or reflection coefficients — it has to produce them — and what it produces is recognisably the staircase with ringing on every plateau and an edge that starts before the wave could have arrived.

What the wave picture is worth

That last figure is the argument of a ladder is not a line, and its conclusion is stronger than “the lumped model is an approximation”.

A transmission line is often introduced as the limit of a ladder of inductors and capacitors as the number of sections goes to infinity. That is true, and it gives entirely the wrong impression of how close a finite ladder gets. Forty sections still ring through every plateau, still smear the edge over a tenth of a delay, and — extrapolating the measured convergence — reaching one per cent on the plateaus would need something close to a thousand sections.

What it would take for a ladder to be a linecomputed by solving, not by drawing at 4 section counts. The plateau error falls as N^-0.54 and the edge's rise time as N^-0.73, the second with a worst residual of 0.92%. Extrapolating the first, a ladder within 1% of the wave answer on its plateaus needs about 961 sections. The extrapolation is drawn dashed because that is what it is.-3-2-10101001ksections in the ladderlog₁₀ of the errorplateau error, N^-0.54rise time ÷ delay, N^-0.731%961 sections, extrapolatedmeasured to heresolved, then checked — two fits, residuals statedmeasured to 40, extrapolated to 961
Fig. 5 How the ladder’s two errors fall as sections are added. The plateau error goes as N^−0.54 and the edge’s rise time as N^−0.73, the second with a worst residual under one per cent. Both are power laws and neither is fast, which is why the wave picture is a different object rather than a convenient summary of a lumped one.

So the staircase is not a shortcut. It is the right description, and the lumped picture is the approximation — which is the opposite of the order they are usually taught in, and the reason this field exists as something other than an appendix to the limits field.

Where the characteristic impedance comes from

One number in this essay has been used without being derived, and it is the one everything else hangs on.

The characteristic impedance is √(L′/C′), and both of those are properties of the cable’s cross section. For a coaxial cable the inductance per metre is (μ₀/2π)ln(b/a) and the capacitance per metre is 2πε/ln(b/a), with a and b the inner and outer radii, so the ratio depends on the geometry only through that logarithm and the impedance is (1/2π)√(μ/ε) ln(b/a). Everything about the size of the cable cancels except the ratio of the two radii.

That is why fifty ohms is a number rather than a range. It corresponds to a particular ratio of radii in a particular dielectric, and a cable of that impedance can be made a millimetre across or a hand across. It is also why the propagation velocity is c/√ε_r and depends on nothing else at all: the product LC′ works out to με regardless of the geometry, so the delay per metre is set by the dielectric alone.

The library derives the two per-metre quantities from the impedance and the dielectric rather than the other way round — L′ = Z₀/v and C′ = 1/(Zv) — because those are the two numbers a datasheet gives. That inversion is what keeps the two routes in this field genuinely separate: the lattice uses the impedance and the delay, the ladder uses the inductance and capacitance, and the only thing they share is the line’s specification.

What is not here

Three things are absent from this page and are worth naming rather than leaving to be noticed.

Loss. Every line drawn here is lossless, so the staircase’s steps are decided entirely by the reflection coefficients. A real cable attenuates, so each round trip is smaller than the geometric series says, and the staircase converges faster than it should. The next essay in this field puts attenuation into the line model for the one claim that needs it — a quarter-wave short circuit is an open circuit only if nothing dissipates — and leaves it out elsewhere.

Dispersion. The velocity here is c/√ε_r, a constant. In a real dielectric it varies with frequency, so the components of an edge travel at different speeds and the edge spreads as it goes. Over a metre this is negligible; over a hundred metres it is the dominant effect.

Anything other than a step. The lattice sums step arrivals. A general waveform is a superposition of steps and could be handled the same way, and is not, because the step is where the argument is.

Where four of this site's models stop being trueIn order: the ideal operational amplifier at 1.42 kHz, a 10 V output at full amplitude at 7.96 kHz, Kirchhoff's laws on 10.0 cm at 3.97 MHz, the ideal 100 nF capacitor at 4.69 MHz. The fifth boundary is an amplitude rather than a frequency and cannot share this axis: a small-signal model is 1% wrong above 7.3 mV, at every frequency there is.101001k10k100k1M10M100M1G10Gfrequency (hertz)the ideal operational amplifier1.42 kHz — a gain of 100 from a 1 MHz part is 1% low herea 10 V output at full amplitude7.96 kHz — above this the output cannot move fast enoughthe ideal 100 nF capacitor4.69 MHz — 1.2 nH of lead makes it 10% wrong hereKirchhoff's laws on 10.0 cm3.97 MHz — the board is one degree long hereeach bar is where the model may be used; the rule at its end is the numbersolved, then checked — each boundary from its own modeland one that is not a frequency: 7.3 mV
Fig. 6 The frequency boundaries the collection has measured. Kirchhoff’s laws on ten centimetres of track run out at 3.97 MHz, and everything on this page is what happens above that mark. The lumped model does not become inaccurate there; it becomes a description of a different object.

One more thing the two routes agree about

There is a second, quieter check available in the staircase and it is worth reading out, because it tests something the divider comparison does not.

The divider comparison tests the limit. It says nothing about the individual steps, and a lattice with a sign error in one of its two reflection coefficients could easily converge to the right place by a wrong route. So the figure also asserts what the far end is doing before the first arrival: at 0.999 of a propagation delay it is at zero, and the assertion is to fifteen decimal places rather than to a tolerance.

Together the two say something quite specific. The staircase gets to the right answer, and it gets there without anything happening before it could have. A model that had the delay wrong would fail the second; one that had the reflections wrong would fail the first; and a model that had both wrong in compensating ways would have to be wrong in a way that is hard to arrive at by accident.

That is the shape this collection reaches for whenever it can. Two checks that fail on different mistakes are worth much more than two checks that fail on the same one, and the pair here is unusually well separated: one is about a limit computed with no time in it, and the other is about what happens in the first five nanoseconds.

One step response, computed twice: from the poles, and by walking the network forwardA damping ratio of 0.22, so the overshoot is 49.2%. The two curves are drawn on top of each other; the panel below is the difference between them, which is the trapezoidal rule's error at 500 steps and reaches 1.70e-3 V.00.50011.50024output (volts), for a 1 V step inthe final valuesolid: from the poles · dashed: stepped forwardtime (milliseconds) above · the same span as a fraction, belowgap between the two routes (volts)1e-71e-61e-51e-41.0m10m1.0e+2m1solved, then checked — residues against 500 trapezoidal stepsthe numerical route is out by 1.7e-3 V
Fig. 7 A step response computed twice — once from the poles by residues, and once by walking the network forward in time — from the transients field. The staircase on this page is the same discipline applied to a circuit whose behaviour no pole expansion describes, and the second route there is the ladder rather than the integrator.