Circuit Response
every model has an edge, and the figure carries it
Concept

Propagation delay — where it appears

The interval between a cause and the response to it, which for a comparator is the time from the threshold crossing to the output moving. It is what lengthens a relaxation oscillator's period beyond the resistor and capacitor that were supposed to set it.

Named by 8 essays across 2 fields — each of them below, with the objects they name alongside it.

A 1 V step onto 1.00 m of 50 Ω line into an open circuit. computed by solving, not by drawing as a sum of 81 arrivals. The source drives 0.8333 V into the line immediately — set by 10 Ω against the line's 50 Ω, and not by the load, which it cannot yet know about. One delay of 4.83 ns later the far end reaches 1.6666 V. The staircase settles at 0.999990 V, which is what the resistive divider gives.

The staircase in time

A source driving a metre of cable does not know what is on the far end of it for 4.83 nanoseconds. What it drives into during that time is decided by the cable's characteristic impedance and nothing else — and when the far end finally answers, the answer comes back as a staircase whose limit is the resistive divider the circuit was going to be all along.

lines · Reflections A series-terminated net holds half a swing for 1.0 delays at 50% along it. computed by solving, not by drawing. What a receiver 50% of the way along one net sees under three terminations, from a lattice evaluated at that point rather than at the ends. The shaded strip is the interval in which a logic input has no defined answer — between 30% and 70% of the swing. The series-terminated net sits in it for 4.83 ns, which is 2(1 − x) delays exactly and is zero only at the far end; the unterminated net sits in it for 4.83 ns and then overshoots by 82%; the parallel-terminated net never does, and draws 60 mA down the line for as long as the level is held.

The resistor at the wrong end

A lattice diagram is read at the two ends of a line, and that is where the two respectable terminations look identical: a clean step, one delay late, at the receiver. Anyone standing halfway along a series-terminated net sees half the swing held for a full round trip, which for a logic input is not a level at all. The interval is 2(1−x) delays exactly, it is zero only at the far end, and the scheme that never has it draws sixty milliamperes for as long as the level is held.

lines · Termination A stub holds the far end at two thirds for twice its own delay. computed by solving, not by drawing. A series-terminated net with a branch on it, marched as waves on a delay grid. Three lines of equal impedance meet at the junction, so each presents the others with Z₀/2 and a wave arriving is reflected by exactly −1/3 with two thirds going on. The far end therefore receives 66.7% of the swing at one line delay instead of all of it, and is held there for 0.400 line delays — twice the stub's own delay of 0.41 ns, being the round trip to its open end and back. The same net without the branch is drawn beside it and settles in one round trip, which is what a series termination is for. Each further round trip of the stub divides what is left of the error by three and turns it over, because the returning wave doubles at the open far end — so the receiver approaches its level alternately from below and from above.

The receiver that is a branch

A lattice diagram has two ends, and an interior receiver is not a point on a net — it is a short piece of track leading off it to a pin, open at the far end. Three lines of equal impedance meeting at a junction present each other with half the impedance, so a wave arriving is reflected by exactly minus a third and two thirds goes on: the far end receives two thirds of the swing and sits there for twice the stub's own delay, whatever the net is terminated with and wherever on it the branch is.

lines · Termination A comparator's delay, at a divider ratio of 0.50. Each nanosecond of comparator delay adds 2.650 nanoseconds to the period — measured as a slope between two delays, both exact multiples of the marching step — against the 2.667 that 4/(1+β) gives and the 2 that counting the delay twice gives. A 50 ns comparator therefore holds the frequency to one per cent only below 75.0 kHz.

The period a delay lengthens

Feed a comparator's output back through a resistor to the capacitor on its own input and the two thresholds stop defending a decision and start setting a period. The closed form is two RC times the log of one plus beta over one minus beta, and a marched circuit recovers it as the step shortens. A comparator that responds fifty nanoseconds late does not add fifty nanoseconds to each half cycle: it adds 4/(1+beta) times the delay to the period, 2.65 here against the 2 that counting it twice gives, because during the delay the capacitor keeps going the way it was going.

applied · Hysteresis Twenty nanoseconds of skew is 0.28% of duty, not 0.40. computed by solving, not by drawing. The duty cycle of a relaxation oscillator whose comparator takes longer to go one way than the other, marched, against the expression that lengthens each half cycle by its own delay. The two part company immediately and by a constant factor of about 1.42: during a delay the capacitor keeps charging past the threshold it already crossed, so the next half cycle starts further out and takes longer, and the two halves partly cancel. At 200 ns of skew on a 2585 ns period the duty is 52.805 per cent where the expression says 54.004. The open circles are the same quantity in closed form — the overshoot is V(1 − (1 − β)e^(−d/τ)) and the next half starts from it — which the march reproduces to parts in ten thousand.

The delay that is two delays

Modelling one comparator delay applied to both transitions makes the two half cycles equal by construction, and the fix is a change of one line. Made, the duty cycle moves by 0.28 per cent for twenty nanoseconds of skew rather than the 0.40 the obvious expression gives, more hysteresis improves the duty cycle and worsens the volt-seconds at the same time, and ten nanoseconds of skew saturates a hundred-turn core in 231 cycles.

applied · Hysteresis Terminated at both ends: no interval anywhere, at 1.65 V of 3.3. computed by solving, not by drawing. The same net as the three-way comparison, with a fourth trace: a series resistor at the driver AND a parallel one at the receiver. Both reflection coefficients are zero, so the wave that arrives at a receiver 50% of the way along is already the final value and there is no second arrival to wait for — the departure after the first edge is 0.0e+0 per cent, which is the arithmetic's floor. What it costs is the level: 1.650 V of 3.3, exactly half, because two equal resistances divide the supply and nothing reflects to double it back. The series scheme in the same place is undefined for 1.00 delays and the unterminated one overshoots by 82 per cent. The hold current is 33.0 mA against the parallel scheme's 60, because the path to ground now has two resistances in it.

Terminated at both ends

A series resistor at the driver and a parallel one at the receiver cost exactly half the swing — 1.650 volts of 3.300 — and no reflection ever gives it back, because there is no reflection. What the half buys is measured rather than asserted: a driver thirty per cent off its assumed impedance rings a series-terminated net by 16.3 per cent and a doubly terminated one by nothing at all, and an interior receiver on a series-terminated net sits in the undefined band for every far-end resistance above 125 ohms, which is Z₀/(1−2b) and contains no length, no driver and no frequency.

lines · Termination At 44.7 Ω the via's area is zero; its reflection is a doublet falling as the 1.99 power of the edge, not the first. computed by solving, not by drawing, as a cascade. A via of 0.25 pF, 1 nH and 0.25 pF on a line of √(L/C) = 44.72 Ω, met by an edge of 59 ps, against the same capacitance alone on the same line. The via's reflection is a doublet — a dip and a bump of equal area — whose largest excursion is 24.4 mV against 166 mV for the capacitance alone. Over edges from 5.9 ps to 295 ps the capacitance's reflection falls as the −0.97 power of the edge and the via's as the −1.99 power: 24.4 mV at 59 ps, 994 µV at 295 ps. The via delays the edge going past it by 22.4 ps, against √(LC) = 22.4 ps.

The via that is a piece of line

A via of half a picofarad of pad and a nanohenry of barrel puts no area under its reflection from a line of √(L/C) = 44.72 ohms, from any edge. It has not vanished. It delays the edge going past it by 22.4 picoseconds, which is √(LC) exactly, and it still reflects: a doublet whose largest excursion falls as the −1.99 power of the edge where a lone capacitance's falls as the −0.97 — 24.4 millivolts for a 59-picosecond edge against 166 for the pads alone, and 994 microvolts for a 295-picosecond one against 35. The balanced via is a short piece of line, and the reflection it leaves is the reflection of its length rather than of its size.

lines · Reflections 20 sections imitating a 1 m line: its delay is 1% long at 318 MHz and its group delay at 185 MHz, and it passes nothing above 1.32 GHz. computed by solving, not by drawing, as a chain of 20 series inductors and shunt capacitors carrying the inductance and capacitance of a metre of 50 Ω line of delay 4.83 ns, terminated in 50 Ω at both ends, beside the Bloch phase of an endless chain, 2·arcsin of ω over the cutoff, a section. The chain's cutoff is the cutoff 2/√(LₛCₛ), 1.32 GHz. Its phase delay is too long by arcsin(x)/x − 1 with x = f over that cutoff, 1% at 318 MHz (x = 0.2417); its group delay by 1/√(1 − x²) − 1, 1% at 185 MHz (x = 0.1404). Well below cutoff the solved chain's delay follows the closed form; nearer it the fifty-ohm terminations, which are not the LC ladder's own impedance there, add a ripple. Ten sections per wavelength is 414 MHz for this chain.

The sections a wavelength needs

A ladder of inductors and capacitors is a line only below its own cutoff, 2/√(LC) of one section, and in the frequency domain how far below can be written down exactly: its delay is too long by arcsin(x)/x − 1 and its group delay by 1/√(1 − x²) − 1, where x is π over the number of sections per wavelength. One per cent of delay needs 13.0 sections per wavelength; one per cent of group delay, 22.4. The rule of ten per wavelength is 1.72 per cent slow in phase and 5.33 in group delay. Twenty sections imitating a metre of cable are a line to a per cent of group delay up to 185 megahertz and pass nothing at all above 1.32 gigahertz.

lines · Distributed vs lumped

Named alongside it

The objects these essays reach for when they reach for this one.

Reflection coefficientLattice diagramTerminationCharacteristic impedanceDesign tradeoffLogic thresholdTransmission lineHysteresisArtificial delay lineCharging exponentialCompanion modelConvergence order

All concepts