Circuit Response
every model has an edge, and the figure carries it
Concept

Lattice diagram — where it appears

The bookkeeping of a step's reflections travelling back and forth along a line, one delay at a time, from which the voltage anywhere on it is a sum. It has two ends in it, so a net with a branch on it needs a junction the diagram cannot express and a wave march instead.

Named by 4 essays across one field — each of them below, with the objects they name alongside it.

A 1 V step onto 1.00 m of 50 Ω line into an open circuit. computed by solving, not by drawing as a sum of 81 arrivals. The source drives 0.8333 V into the line immediately — set by 10 Ω against the line's 50 Ω, and not by the load, which it cannot yet know about. One delay of 4.83 ns later the far end reaches 1.6666 V. The staircase settles at 0.999990 V, which is what the resistive divider gives.

The staircase in time

A source driving a metre of cable does not know what is on the far end of it for 4.83 nanoseconds. What it drives into during that time is decided by the cable's characteristic impedance and nothing else — and when the far end finally answers, the answer comes back as a staircase whose limit is the resistive divider the circuit was going to be all along.

lines · Reflections A series-terminated net holds half a swing for 1.0 delays at 50% along it. computed by solving, not by drawing. What a receiver 50% of the way along one net sees under three terminations, from a lattice evaluated at that point rather than at the ends. The shaded strip is the interval in which a logic input has no defined answer — between 30% and 70% of the swing. The series-terminated net sits in it for 4.83 ns, which is 2(1 − x) delays exactly and is zero only at the far end; the unterminated net sits in it for 4.83 ns and then overshoots by 82%; the parallel-terminated net never does, and draws 60 mA down the line for as long as the level is held.

The resistor at the wrong end

A lattice diagram is read at the two ends of a line, and that is where the two respectable terminations look identical: a clean step, one delay late, at the receiver. Anyone standing halfway along a series-terminated net sees half the swing held for a full round trip, which for a logic input is not a level at all. The interval is 2(1−x) delays exactly, it is zero only at the far end, and the scheme that never has it draws sixty milliamperes for as long as the level is held.

lines · Termination A stub holds the far end at two thirds for twice its own delay. computed by solving, not by drawing. A series-terminated net with a branch on it, marched as waves on a delay grid. Three lines of equal impedance meet at the junction, so each presents the others with Z₀/2 and a wave arriving is reflected by exactly −1/3 with two thirds going on. The far end therefore receives 66.7% of the swing at one line delay instead of all of it, and is held there for 0.400 line delays — twice the stub's own delay of 0.41 ns, being the round trip to its open end and back. The same net without the branch is drawn beside it and settles in one round trip, which is what a series termination is for. Each further round trip of the stub divides what is left of the error by three and turns it over, because the returning wave doubles at the open far end — so the receiver approaches its level alternately from below and from above.

The receiver that is a branch

A lattice diagram has two ends, and an interior receiver is not a point on a net — it is a short piece of track leading off it to a pin, open at the far end. Three lines of equal impedance meeting at a junction present each other with half the impedance, so a wave arriving is reflected by exactly minus a third and two thirds goes on: the far end receives two thirds of the swing and sits there for twice the stub's own delay, whatever the net is terminated with and wherever on it the branch is.

lines · Termination Terminated at both ends: no interval anywhere, at 1.65 V of 3.3. computed by solving, not by drawing. The same net as the three-way comparison, with a fourth trace: a series resistor at the driver AND a parallel one at the receiver. Both reflection coefficients are zero, so the wave that arrives at a receiver 50% of the way along is already the final value and there is no second arrival to wait for — the departure after the first edge is 0.0e+0 per cent, which is the arithmetic's floor. What it costs is the level: 1.650 V of 3.3, exactly half, because two equal resistances divide the supply and nothing reflects to double it back. The series scheme in the same place is undefined for 1.00 delays and the unterminated one overshoots by 82 per cent. The hold current is 33.0 mA against the parallel scheme's 60, because the path to ground now has two resistances in it.

Terminated at both ends

A series resistor at the driver and a parallel one at the receiver cost exactly half the swing — 1.650 volts of 3.300 — and no reflection ever gives it back, because there is no reflection. What the half buys is measured rather than asserted: a driver thirty per cent off its assumed impedance rings a series-terminated net by 16.3 per cent and a doubly terminated one by nothing at all, and an interior receiver on a series-terminated net sits in the undefined band for every far-end resistance above 125 ohms, which is Z₀/(1−2b) and contains no length, no driver and no frequency.

lines · Termination

Named alongside it

The objects these essays reach for when they reach for this one.

Propagation delayReflection coefficientTerminationDesign tradeoffLogic thresholdCharacteristic impedanceModel rangeSource impedanceTransmission line

All concepts