Circuit Response
every model has an edge, and the figure carries it
Concept

Lead compensation — where it appears

A zero placed below a pole in a loop, so that the phase rises over a band near crossover at the cost of low-frequency gain. The phase it adds is fixed in total by the gain it gives up — ninety degree-decades for every twenty decibels — so placing the lead decides only where that phase goes.

Named by 7 essays across 3 fields — each of them below, with the objects they name alongside it.

A loop whose phase comes back, at a gain of 1.0e+7. computed by solving, not by drawing. Three identical poles take the phase to −270°, two lead sections bring it back to −158°, and their own poles take it down again — so ∠L = −180° at 189 Hz, 3.46 kHz and 23.5 kHz. The gain moves the magnitude curve and not those three frequencies, so it decides only which side of each the unity-gain point falls. At 1.00e+7 the crossover is 10.6 kHz, in the recovered band, and the loop is stable.

Stable, and unstable with less gain

A three-pole loop with two lead sections is stable for gains between 1.81 × 10⁶ and 3.36 × 10⁷ and unstable on both sides of that window. Turning its gain *down* is what breaks it. Neither margin can see this, because a phase margin describes the loop at one frequency and a gain margin at one other, and this loop's phase crosses −180° at three: 189 Hz, 3.46 kHz and 23.5 kHz.

feedback · Loop gain 40.0 dB of gain change and 180.0 degree-decades of phase, peaking at 109.8°. computed by solving, not by drawing. The gain and the phase of two leads of 10:1, together, each section buffered from the next. The gain changes by 40.000 dB from one end of the sweep to the other. The area under the phase, integrated on the solve over seven decades beyond the outermost corner, is 180.000 degree-decades, against 180.000 for ninety per twenty decibels of gain change. The peak is 109.806° at 3.16 kHz, below the 131.93° no arrangement of real leads sharing that rise can pass.

The phase a decibel buys

The area under a minimum-phase network's phase, counted in degrees across decades of frequency, is fixed by how far its gain moves from one end of the spectrum to the other: ninety degree-decades for every twenty decibels, however the network is arranged. One 100:1 lead peaks at 78.579 degrees and two 10:1 leads stacked together at 109.806, and both enclose 180.000. The peak is a design decision and the area is a bill — and a network that gives its gain back gives its phase back with it.

frequency · Minimum-phase The capacitor across the upper resistor: 90.9° of margin at 836.5 pF, and less ripple past it. The regulator's phase margin against a capacitor across the upper divider resistor, with the output ripple the 1000 µF reservoir leaves beside it. With no capacitor the margin is 46.47° at a crossover of 9.73 kHz, the output impedance at 10 kHz is 1.95 Ω, the worst rail rejection is 5.79 dB and the ripple 60.62 mV. The margin is greatest, 90.929°, at 836.5 pF — a zero at 6.34 kHz and a pole at 25.4 kHz around a crossover moved to 16.9 kHz — where the output impedance at 10 kHz is 828 mΩ, the worst rail rejection -1.50 dB and the ripple 52.33 mV. At 10 nF the margin has fallen back to 66.34° and the ripple is 35.40 mV.

The capacitor across the upper resistor

The rejection essay said a regulator reproduces its reference times its divider's four, and that a capacitor across the lower divider resistor brings that down to one at high frequency. Measured, the loop peaks the reference's gain to 5.68 near its crossover before any capacitor is added; a nanofarad across the lower resistor raises the peak to 11.2; and the capacitor that brings it down belongs across the upper resistor, where a nanofarad keeps the gain from ever exceeding four. The same capacitor is a lead pair in the loop: 836.5 picofarads takes the phase margin from 46.5 to 90.9 degrees, and ten nanofarads, past that optimum, still holds 66 while cutting the output ripple from 60.6 millivolts to 35.4.

applied · Regulator A capacitor across the upper divider resistor removes the output capacitor's resistance floor. computed by solving, not by drawing. Two series resistances against the capacitance across the upper divider resistor: the smallest the loop tolerates at 45° of margin (lower curve), and the one that gives the smallest droop after a 100 mA load step (upper). With no capacitor they are 939 mΩ and 885 mΩ — the second BELOW the first, which is the conflict this design has: the best transient is one the loop refuses. The floor falls as the capacitor grows and between 500 and 836.5 pF it leaves the sweep altogether, so every series resistance down to a milliohm is stable. Past about 5000 pF the floor climbs back and overtakes the optimum again. The shaded band is where the design a transient wants is one the loop allows.

The floor a second capacitor removes

Two requirements pulling one capacitor found a regulator whose best transient is one it must not be built with: below 939 milliohms of output-capacitor series resistance the loop has under 45 degrees of margin, and the droop is smallest at 885. The capacitor across the upper divider resistor, added for the reference's sake, dissolves that conflict. At 836.5 picofarads the 45-degree floor leaves the sweep entirely — every series resistance down to a milliohm is stable — and the droop falls 40 per cent at the same time. The band of capacitances that do it runs from 100 picofarads to 5 nanofarads, and above it the conflict returns.

applied · Regulator Lead zero at 500 Hz: the lines over-report by at most 3.12° with the loop's phase, and short by up to 20.6°. computed by solving, not by drawing. The error in the phase margin read off the straight lines of an integrator, two poles at 1.00 kHz and a lead section with its zero at 500 Hz and its pole 10 times higher, against where the lines cross unity, measured in decades from the zero. Gaps are placements where the lines are flat at unity or the loop crosses more than once. Read with the loop's own phase the reading is over by at most +3.12°, with the lines crossing −0.01 decades from the zero on a loop with 73.4° of margin, and never over on any loop with 60° or less; it is short by as much as 20.65°. Read with the phase off its straight lines too, on loops with 60° or less, it is never over.

The zero that lifts the lines

A phase margin read off the straight lines of an all-pole loop can only be short, and the proof takes three steps. A lead section breaks two of them: a zero's response lies above its lines, and between a zero and its pole the phase rises. The two breaks pull opposite ways, and measured across every placement of the crossing, in every sweep drawn, they leave an over-report of at most 6.58°, on a loop with 87.5°; on loops with sixty degrees or less it never exceeds 1.52°. The phase sketch is another matter: with the lines crossing at a lead zero above the plant's corner, it reports 17.91° on a loop with 1.17°.

frequency · Asymptotic approximation Losing capacitance to bias raises this loop's margin; the corner that binds is the ceramic at full value. computed by solving, not by drawing. Phase margin of the five-volt regulator with a 5.00 mΩ ceramic output capacitor, against the capacitance that capacitor keeps at the working voltage, from the full 10 µF down to 1.5 µF, for five capacitors across the upper divider resistor. With none, the margin climbs from 18.0° at full value to 43.6° at 15% kept, so the lost capacitance is stabilising rather than the reverse. 630 pF holds at least 49.7° across the whole range. 836.5 pF, the value that removed the resistance floor at the nominal capacitance, gives 48.8° at full value and 44.3° at 15%: the capacitor that has lost the most is the one it fails on.

The capacitance the bias takes away

A ceramic output capacitor has a few milliohms of series resistance, which a capacitor across the upper divider resistor made legal, and a capacitance that falls with the voltage across it — a ten-microfarad part at five volts is two microfarads to a small signal. Swept from the full ten down to that fifth, the regulator's margin does not collapse. It rises: with no divider capacitor from 18.0° to 38.5°, because the output pole climbs away from the amplifier's. The corner that binds is the capacitor at full value. One divider capacitor, 423 to 808 pF, holds 45° at every capacitance between. The 836.5 pF that removed the resistance floor sits just above that band, and the lost capacitance is paid for in droop: 103 mV at full value, 202 mV at a fifth.

applied · Regulator At full capacitance the margin falls with the load, and below a tenth of an ampere no divider capacitor gets it past 36.9°. computed by solving, not by drawing. Phase margin of the five-volt regulator with a 5 mΩ ceramic keeping 10 µF, against the load current from 5 mA to 1 A, for four capacitors across the upper divider resistor. 630 pF, which held 45° at every capacitance at an ampere, gives 49.7° at 1 A and 36.0° at 5 mA. With no capacitor the margin at 5 mA is 0.1°. The dotted level is 36.87°, the most phase a zero and a pole four times apart can ever lead by, and every curve ends under it. The crossover stays between 12.9 kHz and 13.2 kHz over the whole range.

The lead a divider can give

At an ampere one capacitor across the upper divider resistor holds this ceramic regulator above 45° at every capacitance the part keeps. At 5 mA nothing does. The crossover stays at 13 kHz while the output pole falls from 3.20 kHz to 31.8 Hz, so the loop arrives at unity with every lag it has and the only phase left is the lead the divider capacitor makes — and that lead has a ceiling, arcsin((G − 1)/(G + 1)), set by the divider's ratio alone. For a five-volt output from a 1.25 V reference it is 36.87°, and the best capacitor reaches 36.83°. Over the rectangle from 5 mA to an ampere and ten microfarads to two, the best single capacitor gives 32.4°. Putting 416 mΩ back in series with the ceramic restores 45° over all of it, and lowers the droop rather than raising it.

applied · Regulator

Named alongside it

The objects these essays reach for when they reach for this one.

Phase marginLoop gainDesign tradeoffEquivalent series resistanceTransient responseBode plotMinimum-phaseAll-passAsymptotic approximationCrossover frequencyEncirclement countExcess phase

All concepts