The load that rings with the line

The boundary that is a rise time marched the far end of ten centimetres of 50 Ω track as the exact staircase of reflections it is, driven by a ramp, and found the lumped-element boundary to be a rise time with no clock rate in it: one per cent of overshoot at a 40.0 ns edge, about thirty of the track’s round trips. Its load was a resistor, so every reflection was a fixed fraction of the wave that caused it and the staircase was a geometric series. It named the case that breaks that: a load that is a capacitance, like every logic input on every board, where the reflection is not a number and the overshoot becomes a ring.

This essay puts the capacitance on the end. The track is marched by its characteristics — a forward wave and a backward one, each arriving a transit later — so that the load’s own equation can be stepped at the far end rather than replaced by a coefficient. Three things come out. The capacitance makes the overshoot worse and moves the boundary to slower edges, by an amount that depends on how the capacitance compares with the track’s own. The lumped model, which failed on the bare track, comes back as the load grows — not as a model of the track, but as a model of the ring. And the one arrangement that removes the problem at every capacitance is on the other end of the line.

The reflection that is not a number #

With a resistor at the far end, each wave arriving there is multiplied by $1 + \rho_L$ and a fraction $\rho_L$ turns back, and $\rho_L = (R_L - Z_0)/(R_L + Z_0)$ is 0.6 for 200 Ω on 50 Ω. With a capacitor across the resistor there is no such fraction. At the first instant the capacitor is a short and reflects the wave inverted; a few $Z_0 C$ later it is open and reflects it upright; and in between it reflects something that changes with time. So the far end’s equation has to be solved as it goes: the incident wave drives a current into the parallel resistor and capacitor, the capacitor charges, and what does not go in comes back.

The march does exactly that. The track — 10 cm of FR-4, a transit of 0.70 ns — is a pair of delay lines. At the source end the outgoing wave is fixed by the source voltage, its 10 Ω and whatever wave has just arrived back; at the far end the incoming wave charges the load, whose equation $C\,dv/dt = 2f/Z_0 - v(1/Z_0 + 1/R_L)$ is stepped by the trapezoidal rule eighty times a transit; and the reflected wave is whatever the load’s voltage leaves of the incident one. With no capacitance the far end reduces to the earlier essay’s staircase exactly and settles on the resistive divider, 0.952 V, to a part in a million.

With 10 pF on it, the one-nanosecond edge is held down briefly by the capacitor and then overshoots by 47.5 per cent, against 40.0 bare, and rings. The ring is near 174 MHz, and that number is not a property of the line alone. The track has 35 nH of inductance and 14 pF of capacitance of its own — $Z_0 T$ and $T/Z_0$ — and the ring is close to the frequency those make with the load’s 10 pF added: $1/(2\pi\sqrt{L(C_{line} + C_{load})})$. With 2 pF the overshoot is 42.1 per cent and the ring nearer 213 MHz; with 20 pF, 47.8 per cent and 146 MHz. The capacitance slows the ring and deepens it, and all of it settles on the same divider, since a charged capacitor carries nothing.

The boundary becomes a rise time and a capacitance #

The earlier essay’s boundary — the edge at which the overshoot falls to one per cent — was 40.0 ns for this track, twenty-nine round trips, set by how much of the staircase an edge could hide.

Bisected on the characteristic march, the one-per-cent boundary is 39.9 ns with no capacitance — the earlier essay’s figure, found by a different route — and it rises as the load grows: 41.0 ns with 1 pF, 45.2 with 5, 50.4 with 10, 60.8 with 20 and 83.4 with 50. A typical input of a few picofarads moves it by a few per cent. A bus with several inputs on it, or a connector and a cable stub, moves it by a factor of two.

The ten-per-cent boundary moves differently. It first falls — 4.23 ns bare to 3.78 with 5 pF — because a small capacitance rounds the first step of the staircase and takes the sharpest part of the overshoot off it, and then rises, to 7.64 ns with 50 pF, as the ring it makes grows slow enough to survive a moderate edge. That is the capacitance playing two parts at once: a filter on the staircase’s steps, and a resonator with the track’s inductance.

So the boundary is no longer a rise time alone. The earlier essay’s version — the edge must be slow against the round trip — still holds for the bare track. With a capacitance the edge must also be slow against the ring the capacitance makes with the track, and whichever of the two is slower decides. For a 10 cm track on a board the crossover is at about the track’s own 14 pF: below it the round trip decides; above it, the load does.

The lumped model comes back #

Kirchhoff’s own frequency measured the lumped model failing as frequency rose, and the earlier essay measured it failing as edges quickened. On the bare track a 1 ns edge is forty times faster than the edge it needs. What the load does to that verdict is worth measuring directly, as the gap between two waveforms.

For each load the same circuit is marched twice: by characteristics, and as the lumped model a designer would draw — the track’s whole inductance and capacitance as one inductor and one capacitor — on the netlist. The largest difference between the two far-end waveforms is 55.0 per cent of the settled voltage with no load capacitance: the lumped model misses the staircase entirely, as it must at an edge this fast. It falls with every added picofarad — 43.9 per cent at 5 pF, 33.6 at 10, 24.6 at 20, 10.7 at 50, 4.9 at 100 — and at 200 pF it is 2.2 per cent.

The reason is the one the ring frequency gave. With a heavy load, the track is a small inductance in front of a large capacitor. The ring that capacitor makes with the track’s inductance is slow — tens of nanoseconds per cycle at 200 pF, against a 1.4 ns round trip — and over a single slow cycle the track’s distributed nature does not show: a small inductance behaves as an inductance whether it is spread out or not. So the lumped model returns, as a model of the ringing between the track’s inductance and the load’s capacitance, which is the thing that now decides the waveform. It never became a good model of the track. The load made the track irrelevant to the part of the waveform that matters.

That is a useful reversal to have. A heavily loaded short bus is often modelled as a single LC and the model is right; a lightly loaded one modelled the same way is wrong by half its voltage. The criterion is the ratio of the load’s capacitance to the track’s own, which a designer can compute from a length and a characteristic impedance.

Three marches of one case #

The earlier essay recorded, as an open question, that the honest comparison is between two time-domain waveforms rather than between a waveform and its own limit. Here are three, for one case.

A 3 ns edge into 200 Ω and 10 pF, marched three ways. By characteristics the far end overshoots by 22.82 per cent. As twenty-four lumped sections — the track cut into pieces each 29 ps long, a hundredth of the edge — it overshoots by 23.16 per cent, and the whole waveform agrees with the characteristic march to 6 mV: the two are one circuit computed two ways, and the agreement is the check on both. As one section it overshoots by 29.54 per cent, and rings visibly longer and at a slightly different frequency.

The seven points between one section and many are the frequency-domain gap Kirchhoff’s own frequency reported between a line and its lumped model, seen as a waveform on the axis an oscilloscope has. The sections a wavelength needs asked how many sections an LC ladder needs to stand in for a line at a frequency; twenty-four is comfortably enough here, and one is enough only once the load has made the ring slow.

A matched source turns the ring into a delay #

The ring needs two reflections: the load’s, which a capacitance guarantees, and the source’s, which a strong driver provides. Remove the second and there is nothing to ring.

Driven from 10 Ω into a bare capacitance — a logic input with nothing else — the far end overshoots by 67 per cent with no capacitance and 69 per cent with 5 pF; with 20 pF, 63 per cent, and rings for tens of nanoseconds. Driven from 50 Ω, the line’s own impedance, it overshoots by under a tenth of a per cent at every capacitance. The wave reflected from the capacitor goes back to a source that absorbs it, so the far end sees one incident wave and the capacitor charging from it through the line’s impedance. It rises monotonically to the source’s voltage, taking about $2.2\,Z_0 C$ beyond the edge: 2.36 ns for 20 pF, against 2.2 ns from the formula.

The capacitance has not gone away. It has been converted from a ring into a delay, which a timing budget can carry and a threshold cannot be fooled by twice. That is the argument for series termination at the driver, and the resistor at the wrong end is its companion, measuring what a termination placed where the load is does instead. For a capacitive load the source end is where the resistor belongs, because the load end has nothing resistive to match against.

What a fan-out costs #

The numbers turn into a design decision on the commonest net there is: one driver, a short track, several inputs. Four logic inputs at 5 pF each put 20 pF on the end of 10 cm. Driven from a strong 10 Ω output, the one-per-cent boundary is then 60.8 ns — an edge no modern driver produces — and a 1 ns edge overshoots by 47.8 per cent. The overshoot is not a curiosity at that size: on a 3.3 V net it is 1.6 V above the rail, well past the point at which an input’s protection conducts and injects the excess into the substrate.

There are three honest responses, and the measurements price each. Slowing the edge to the boundary costs sixty nanoseconds of every transition, which few designs can pay. Shortening the track helps less than it seems, because with a heavy load the boundary is set by the ring the capacitance makes with the track’s inductance, and a shorter track has less inductance but the same 20 pF: the ring speeds up and the boundary falls only roughly as the square root of the length, the ring’s period going as the square root of the inductance. Matching the source costs one resistor and about $2.2 Z_0 C$ of delay, 2.4 ns for 20 pF, and leaves no overshoot at all — which is why a series resistor at a strong driver is the standard answer and why its value is the line’s impedance less the driver’s own.

The ring also has a cousin in reflectometry. The dip whose area is fixed found a picofarad on a line appearing in a reflected edge as a dip whose area is $Z_0 C/2$ whatever the edge’s speed. That is the same capacitance seen from the source, one transit earlier, before it has had time to ring with anything: an area in the reflection, where at the far end it is a delay or a ring depending on what the source does with the reflection when it arrives.

How the numbers were obtained #

The line is marched by the method of characteristics: the forward wave launched at the source and the backward wave launched at the load are each stored and read back one transit later, the source end is solved algebraically from the source voltage, its resistance and the arriving wave, and the load end integrates the parallel resistor and capacitor’s equation by the trapezoidal rule with the incident wave interpolated across each step, at forty to eighty steps a transit. With no capacitance the march is the resistive staircase exactly. The boundaries are bisected on the march in the logarithm of the rise time, each case run for at least sixty transits and six ring periods. The lumped comparisons march the one-section and twenty-four-section netlists by the trapezoidal rule at 6,000 to 8,000 steps; the gap is the largest absolute difference over the run.

This essay also corrected the earlier one. Its figures had put the bare track’s one-per-cent boundary at 41.6 ns and the overshoot at a 100 ns edge at 0.443 per cent; the characteristic march gave 39.9 and 0.400, and a hand calculation — the staircase’s excess area past its first interval, 0.544 of a transit, over the edge — sided with the march. The earlier essay had averaged the step response across the ramp at 600 points, which at slow edges is a staircase standing in for a ramp; it now integrates the ramp exactly, and its numbers are 40.0 ns and 0.399 per cent.

What it leaves out #

The input’s own inductance and resistance. A logic input is a capacitance behind a bond wire and a package lead, a few nanohenries, and behind a protection structure with resistance of its own. The inductance adds a second, faster resonance; the resistance damps both.

Loss in the track. The march is lossless. A lossy track damps the ring as it propagates, and the edge the loss delivers measured what loss does to an edge’s shape on its own.

Several loads along the track. A bus has its capacitances distributed, each one a small reflection of its own at its own position, and the staircase becomes a pattern of partial reflections rather than a single ring.

Still open: the boundary as a length, several loads, and the capacitance a termination leaves #

The same boundary read the other way. Everything here fixes the track and sweeps the edge or the load. A design has the opposite question — given the edges the parts make, how long may a track be? — and it is the same curve read backwards. The earlier essay’s boundary gives a length in millimetres per nanosecond of edge directly, and the source’s mismatch, which this essay found removing the ring altogether when it is zero, should decide whether there is a limit at all.

Loads spread along the track. Several capacitances at intervals lower the track’s effective impedance and slow its velocity between them, and at some spacing the bus behaves as a new line with its own impedance. Where that happens is a march with several load equations in it.

A parallel termination with a capacitive input. A resistor to ground at the far end, matched to the line, absorbs the first wave — but the input’s capacitance is still in parallel with it, and the combination is matched only at low frequency. How much of this essay’s ring survives a parallel termination is a question terminated at both ends did not ask with a capacitance present.