The heavier input that allows a longer track

How long a track may be read the lumped-element boundary the way a layout is designed: given the edge, how long may the track be? For 50 Ω track driven from 10 Ω, a 1 ns edge stayed inside one per cent of overshoot for 2.51 mm into 200 Ω and 1.80 mm into an open end, and every nanosecond of edge bought proportionally more. The rule had a closed form in the product of the two ends’ reflection coefficients, and the driver’s resistance was its most important term: a matched driver had no limit at all.

Every load in that essay was a resistance. Its first open question was the load a digital track actually has: a CMOS input, which is nearly an open end with a few picofarads across it. The load that rings with the line had already found that a capacitance on the far end turns the reflection from a number into a ring, and the boundary that is a rise time that it moves the boundary to slower edges. The question here is the layout’s: read as a length, does a capacitive input make the limit shorter in proportion to its capacitance? It does not, and for a heavy load it does the opposite.

A valley, and then a rise #

The track is the earlier essay’s: 50 Ω on FR-4, a wave travelling 14.3 cm a nanosecond, driven from 10 Ω by a 1 V edge rising in 1 ns. The far end is an open end with a capacitance across it, marched by characteristics with the capacitor’s own equation stepped in time, and the longest length whose far end overshoots by less than one per cent is bisected on the march.

With no capacitance the limit is the open end’s 1.80 mm. A third of a picofarad brings it to 1.28 mm, half a picofarad to 1.04, one to 0.88, and it reaches its least, 0.86 mm, near 1.5 pF. Then it turns: 0.96 mm at 3 pF, 1.15 at 5, 1.68 at 10 — nearly back to the bare limit — 2.71 at 20, 5.70 at 50 and 10.9 mm at 100 pF. Between 20 and 100 pF it grows as the 0.87 power of the capacitance, close to in proportion. From a 25 Ω driver the same shape is shallower and the rise far steeper: a least of 2.59 mm at half a picofarad and 79.8 mm at 100 pF.

So a designer who has reasoned that a heavier input is a worse load for a fast edge is right for small capacitances and wrong for large ones, and the turn comes at a capacitance — a picofarad or two — that is an ordinary CMOS input’s. An input of 10 pF, a multi-load bus or an input with protection diodes, allows nearly as much track as an open end; one of 100 pF allows six times as much.

Three waveforms on one length #

The turn makes sense once the far end’s waveform is looked at for three loads on the same track.

On 3 mm of track the bare open end climbs the staircase of reflections the earlier essays measured and overshoots by 1.67 per cent — 3 mm is longer than its 1.80 mm limit. With 2 pF across it the far end rings instead, at the frequency the track’s own 1.05 nH of inductance makes with the capacitance, and overshoots by 3.08 per cent: worse. With 50 pF it does not ring at all. The far end charges, smoothly, through the driver’s resistance, and the overshoot is under a thousandth of a per cent.

The three are one circuit seen at three loads. A track short against the edge, ending in a capacitance, is to a good approximation a series inductor — the track’s — between the driver’s resistance and a shunt capacitor — the track’s own plus the load’s. That circuit’s damping is

$$\zeta = \frac{R_s}{2}\sqrt{\frac{C}{L}},$$

and it is 0.24 for 3 mm into 2 pF and 1.10 for 3 mm into 50 pF. A heavy capacitance makes the circuit better damped, not worse, because the damping grows as the square root of the capacitance while the ring’s frequency falls. The 2 pF ring is underdamped and fast enough that a 1 ns edge excites it; the 50 pF one is overdamped, and an overdamped circuit cannot overshoot at all.

At heavy loads the limit is a damping #

If the series circuit is the right model, the one-per-cent length at a heavy load should be set by its damping alone — a fixed $\zeta$ — and the length should scale as $R_s^2C$.

It is. From a 10 Ω driver the damping at the one-per-cent length is 0.565 at 5 pF, 0.659 at 10, 0.733 at 20, 0.798 at 50, 0.815 at 100 and 0.819 at 200 — settling. From 25 Ω it is 0.669 at 5 pF and 0.789 from 50 pF upwards. Once the load capacitance dwarfs the track’s own — which for a few millimetres of track is a fraction of a picofarad — the track is an inductor and nothing else, the series circuit is exact, and the limit is the length at which that circuit’s damping falls to about 0.8, where a 1 ns edge first raises one per cent of overshoot.

That turns the rule into a formula with no round trip in it. Setting $\zeta$ to its fixed value with the track’s inductance $Z_0\ell/v$ and a load $C_L$ gives

$$\ell_{\max} \approx \frac{R_s^2\,C_L\,v}{4\zeta^2 Z_0},$$

which for 10 Ω, 100 pF and $\zeta = 0.815$ is 10.8 mm against the bisected 10.9. The earlier essay’s rule, $\varepsilon t_r v(1-q)/2(-q)$, is the light-load limit; this is the heavy-load one, and the valley between them is where neither applies — where the track is still a line to the edge but the load is already large enough to ring with it.

A slower edge buys less than it did #

The earlier essay’s constant was 2.5 mm of track per nanosecond of edge: the limit proportional to the edge, because the overshoot was a matter of round trips per edge. A heavy input breaks that proportionality.

Into a bare open end the longest track is 0.18 mm for a 0.1 ns edge, 1.80 for 1 ns and 17.96 for 10 — proportional, slope 1.00. Into 20 pF it is 2.16 mm for 0.1 ns, 2.71 for 1 ns and 8.80 for 10: over two and a half decades of edge it grows as the 0.40 power, and for the fastest edges it barely moves at all. The heavy load’s limit is set by the damping of a lumped circuit, and a slower edge helps a lumped circuit only by giving its ring less to excite: for an overdamped circuit the edge is irrelevant, and for a slightly underdamped one a slower edge reduces the overshoot gradually rather than in proportion.

The crossover has a practical reading. For a fast edge — a few hundred picoseconds — the heavy input allows more track than the bare one: 2.16 mm against 0.18 at 0.1 ns. For a slow edge it allows less: 17.7 mm against 35.9 at 20 ns. Somewhere between them the two are equal, and that is the edge at which a capacitive input stops being the worse load and starts being the better one. At 5 pF the crossing is between 0.2 and 0.5 ns; at 20 pF between 1 and 2 ns.

A weaker driver is the clean one #

The formula’s other variable is the driver’s resistance, and it enters squared.

Into a 20 pF input the longest track is 0.20 mm from a 2 Ω driver, 0.82 from 5 Ω, 2.71 from 10, 10.3 from 20 and 67.2 mm from 40 Ω. Into a bare open end it is 1.50, 1.60, 1.80, 2.40 and 7.19 mm over the same drivers — rising too, as the earlier essay’s mismatch curve did, but slowly. Between 5 and 20 Ω the heavy input’s limit grows as the 1.8 power of the driver’s resistance.

The instinct this contradicts is a strong one. A designer with a heavy capacitive load and a fast edge usually reaches for a stronger driver, to charge the capacitance faster. Into a capacitive input on a track, a stronger driver removes the very resistance that damps the ring, and the track it may drive shrinks roughly as the square of its resistance. A series resistor at the driver — the source termination the earlier essays found useful for a resistive load — is doubly useful here: it moves the driver towards the line’s impedance, which the earlier essay’s rule rewards, and it damps the lumped ring, which this one does.

A board, worked #

A worked case shows how much the driver’s resistance is worth. A track of 20 mm carries a 1 ns edge to a load of 10 pF — an input with protection, or two inputs side by side. From a 10 Ω driver the longest track inside one per cent is 1.68 mm, and on 20 mm the far end overshoots by 28 per cent. The usual repair is a series resistor at the driver. Adding 10 Ω, for 20 Ω in all, raises the limit to 5.94 mm and cuts the overshoot to 12.4 per cent; adding 23 Ω, for 33 in all, raises it to 18.7 mm and the overshoot to 1.34 per cent; adding 37 Ω, for 47, raises it to 95.7 mm and the overshoot vanishes.

The series resistor is doing two jobs at once. It brings the driver towards the line’s 50 Ω, which the earlier essay’s rule rewards, and it damps the lumped ring, which this essay’s does. At 47 Ω it is nearly matched to the line and the load is heavy enough that the circuit is overdamped; either reason alone would have helped, and together they make the 20 mm track unremarkable. What it costs is time: the far end now charges through 47 Ω into 10 pF plus the track’s own capacitance, a time constant of about six-tenths of a nanosecond added to the edge, which for a 1 ns signal is a price worth paying and for a 100 ps one is not.

The same arithmetic warns against the opposite repair. A designer who sees the 28 per cent ring and concludes that the driver is too weak for 10 pF, and replaces it with a stronger one, has moved the wrong way along the driver figure: a 2 Ω driver into the same load allows a fraction of a millimetre.

Why a picofarad or two is the worst #

The valley’s position can be read from the two regimes’ meeting. On the light side, the track is a line and its limit is the earlier essay’s: a length per nanosecond of edge, shortened as the load’s capacitance makes the far end’s reflection reactive. On the heavy side, the track is an inductor and its limit grows as $R_s^2C$. The light-side limit falls with capacitance and the heavy-side one rises, and the least is where they cross — where the load is just heavy enough to ring with the track’s inductance and not heavy enough for the driver to damp it.

For a 10 Ω driver that crossing is near 1.5 pF; for 25 Ω, half a picofarad, because a stronger damping term reaches the heavy-side regime sooner. A designer cannot easily move the input’s capacitance, but can move the valley by moving the driver’s resistance, and from 25 Ω the valley is shallow: 2.59 mm at its least against 2.89 bare. A modest source resistance turns the worst case from half the open end’s limit into nine-tenths of it.

Where the rule comes from, and where it stops #

Both rules are the same march read in two regimes. At light loads the far end sees the line: waves arrive, reflect off an open end, and the overshoot is a staircase whose steps are round trips, so the limit is a length per nanosecond of edge set by the two reflection coefficients. At heavy loads the far end sees a lumped circuit: the capacitance is so much larger than the track’s own that the wave’s arrival is irrelevant, and the track is just the inductance between the driver and the load. The limit there is a damping, set by the driver’s resistance and the load.

The valley between them is the hazard. An input of a picofarad or two is too light to make the circuit lumped and heavy enough to ring with the track at a frequency a nanosecond edge excites, and there the longest track is less than half the bare open end’s. That is exactly the capacitance of a single CMOS input, which is why point-to-point digital tracks to one receiver are where ringing is most often seen and least often expected.

Two cautions on the formula. It holds only while the track is short against the edge — while the track is a lumped inductance — and the heavy-load lengths here, ten millimetres at 100 pF, are well inside that for a 1 ns edge but would not be for a 100 ps one. And it assumes the load is a pure capacitance; an input’s protection diodes clamp the overshoot that a long track would otherwise produce, which hides the ring from a measurement of overshoot while it still costs timing.

How the numbers were obtained #

The track is marched by the method of characteristics, as in the earlier essays: forward and backward waves on a lossless 50 Ω line, the source a ramp behind its resistance, the far end an open end with a capacitance stepped by the trapezoidal rule with the incident wave interpolated across the step. The march runs long enough to catch the largest excursion, six ring periods of the track’s inductance with the total capacitance or sixty round trips, whichever is longer. The longest track for a tolerance is bisected in the logarithm of the length. The damping figure computes $(R_s/2)\sqrt{C/L}$ from each bisected length, with L the track’s inductance and C its capacitance plus the load’s.

What it leaves out #

The receiver’s own structure. A CMOS input is a capacitance in parallel with clamp diodes and, inside the package, a bond wire’s inductance. The bond wire adds to the track’s inductance and the diodes clamp the far end’s excursions to the rails, so a real input both rings more readily and hides it better.

Several inputs along the track. A bus with several receivers tapped along it is a line loaded at intervals, and its effective impedance and velocity both fall. The light-load rule then applies with a lower impedance and a slower wave, and the heavy-load one with the total capacitance; where the crossover sits for a distributed load is a different question.

Still open: branches, the driver whose resistance moves, and a load that is distributed #

A track that forks. A branch sends part of each wave on and reflects part back, and each branch end with its own capacitance rings at its own frequency. Whether the longest branch a given edge tolerates is set by the round trip to the fork, by the lumped ring of each branch, or by the two branches’ rings beating, is the stub question the earlier essay named, with this essay’s damping added.

A driver whose resistance depends on its level. A CMOS output’s resistance changes as it switches, low in the middle of a transition and higher at the ends, so the damping it supplies to a capacitive load is not one number. Whether the effective resistance for this essay’s damping is the output’s resistance at the end of the edge, where the ring is excited, is a measurement on a real driver’s curve.

A load spread along the track. At the limit of many small inputs the load is a capacitance per unit length, which lowers the track’s impedance and slows its wave rather than loading its end. Whether the valley survives — whether a distributed load has a worst density the way a lumped one has a worst capacitance — is the continuum version of this essay.