Feedback, and the margin

The sensor an integrator does not see

A sensor's capacitance at an inverting stage's summing junction sits across a node that rises like an inductance, and makes a resonance: 10 nF lifts the node 2.50-fold at 39.8 kHz, the lift is the resonance's Q, and the loop's margin falls from 90° to 24.8°, and to 8.0° at 100 nF. The same capacitance at an integrator's node sits across a resistance — the shelf, 1/(2π·GBW·Cf) — and the shelf does not move, because the capacitance enters the open node and the loop gain together and cancels. With an ideal output the integrator's margin is 90.91° at every sensor from 1 pF to 100 nF. What it does see is its amplifier's output resistance: 50 Ω driving the feedback and sensor capacitors in series is a pole, worst when the two are equal, 58.3° at 10 nF, and it recovers on both sides.

Assumes: The node that is at ground for a while · What is left at crossover

The shelf a capacitor makes looked into two summing junctions on the same one-megahertz amplifier. An inverting stage’s node, with a resistor as its feedback element, rises a decade per decade from a tenth of an ohm to the two resistors in parallel, 909 Ω. An integrator’s node, with a capacitor as its feedback element, does neither: its loop gain has no frequency in it over the band the capacitor dominates, so the node sits flat on a shelf, Rin/(1+2π GBW CfRin)R_{in}/(1 + 2\pi\,\mathrm{GBW}\,C_f R_{in}), 15.67 Ω with a kilohm in and ten nanofarads of feedback. It is worst at direct current, where the capacitor is an open circuit and there is no loop.

That essay ended on the case that makes the difference practical. A charge amplifier reads a sensor that is itself a capacitance — a piezoelectric element, a photodiode’s junction, a long cable — and the sensor sits directly on the summing junction. A flat impedance and a capacitance make a corner. A rising impedance and a capacitance make a resonance. So the same sensor should do different things to the two circuits, and this essay measures how different, and whether it is only the node or the whole loop that notices.

A resonance at one node, a corner at the other

Both circuits keep the earlier essay’s values: a kilohm in, ten kilohms or ten nanofarads of feedback, an amplifier of one megahertz with a gain of 10510^5 and fifty ohms of output resistance. A capacitance is added from the summing junction to ground and the node is measured by driving a current into it and reading the voltage.

10 nF at the node lifts the inverting stage's virtual earth 2.50-fold at its resonance, the integrator's 1.14-foldcomputed by solving, not by drawing. The impedance looking into the summing junction of an inverting stage (1 kΩ in, 10 kΩ feedback) and an integrator (1 kΩ in, 10 nF feedback) on the same 1 MHz amplifier, bare (dashed) and with 10 nF of sensor capacitance from the node to ground (solid). The inverting stage's node rises as an inductance, and a capacitance across an inductance is a resonance: its node reaches 909 Ω at 39.8 kHz, 2.50 times the bare node there. The integrator's node is a resistance, the shelf of 15.9 Ω, and a capacitance across a resistance is a corner: the loaded node is at most 1.136 times the bare one, and only where the amplifier's own output resistance is part of the loop.1m10m100m1101001k1101001k10k100k1M10M100Mfrequency (hertz)impedance looking into the summing junction (ohms)the shelf, 15.9 Ωinverting, bareinverting, 10 nFintegrator, bareintegrator, 10 nFsolved, then checked — a current driven into each nodea resonance, or a corner
Fig. 1 The summing-junction impedance of an inverting stage (1 kΩ in, 10 kΩ feedback) and an integrator (1 kΩ in, 10 nF feedback) on one 1 MHz amplifier, bare (dashed) and with 10 nF from the node to ground (solid). The inverting stage’s node reaches 909 Ω at 39.8 kHz, 2.50 times the bare node there. The integrator’s loaded node is at most 1.14 times its bare one.

The inverting stage’s node, which rose smoothly to its 909 Ω ceiling, now has a hump. With ten nanofarads on it the node reaches the full 909 Ω at 39.8 kHz, where the bare node was only two fifths of that: 2.50 times as high. The integrator’s node barely changes. Its shelf is where it was, and nowhere is the loaded node more than 1.14 times the bare one.

The reason is the one the node that is an inductance made central. A node whose impedance rises in proportion to frequency is an inductance, here L=R/(2πfcl)L = R/(2\pi f_{cl}) with RR the 909 Ω ceiling and fclf_{cl} the 90.9 kHz at which the loop gives out, which is 1.59 mH. The ceiling is a resistance in parallel with it. Add a capacitance and the node is a parallel resonant circuit, which at its resonance is exactly the resistance: 909 Ω, at 1/(2πLC)1/(2\pi\sqrt{LC}). The bare node at that frequency was ωL\omega L, so the lift is R/ωLR/\omega L, which is the resonance’s quality factor Q=RC/LQ = R\sqrt{C/L}. For 1 nF that is 0.72 at 126 kHz; for 10 nF, 2.28; for 100 nF, 7.2 at 12.6 kHz. The figure’s slider steps through those, and the measured lifts, 1.28, 2.50 and 7.22, follow the Q once it is well above one.

The integrator’s node is not an inductance but a resistance, and a resistance with a capacitance across it has a corner and no resonance. That is why nothing happens to its shelf — and the next section says why the shelf does not even move.

What the loop makes of it

A node’s impedance is one reading of the loop. The margin is another, and it is the one that decides whether the circuit rings.

A sensor's capacitance takes the inverting stage from 90° to 8°; the integrator's least is 58.3°, where the sensor equals its capacitor. computed by solving, not by drawing. Phase margin of each loop, cut at the amplifier's input and driven there, against a capacitance from the summing junction to ground, 1 pF to 100 nF. The inverting stage (solid) goes 90.0° → 64.9° at 1 nF → 24.8° at 10 nF → 8.0° at 100 nF: the capacitance and the two resistors in parallel put a pole into its feedback factor. The integrator with an ideal output (dotted) holds 90.91° at every capacitance, since its feedback factor becomes Cf/(Cf + Cs), a constant. With the amplifier's 50 Ω of output resistance (dashed) it dips to 58.3° at 10 nF and recovers to 76.8° at 100 nF: the output drives Cf in series with Cs, a pole that is highest when either is small, and the loop crosses over lower as Cs grows.
Fig. 2 Phase margin of each loop against the capacitance at the summing junction, 1 pF to 100 nF. The inverting stage (solid) goes from 90.0° to 64.9° at 1 nF, 24.8° at 10 nF and 8.0° at 100 nF. The integrator with an ideal output (dotted) holds 90.91° everywhere; with 50 Ω of output resistance (dashed) it dips to 58.3° at 10 nF and recovers to 76.8° at 100 nF.

The inverting stage’s margin collapses. At 1 nF it is 64.9 degrees, at 10 nF 24.8, at 100 nF 8.0. The mechanism is the familiar one for an input capacitance: the feedback factor was Rin/(Rin+Rf)R_{in}/(R_{in} + R_f), a constant, and the capacitance in parallel with RinR_{in} gives it a pole at 1/(2π(Rin∥Rf)Cs)1/(2\pi (R_{in} \parallel R_f) C_s). The margin is ninety degrees less that pole’s lag at the crossover, and the figure checks that closed form against every one of its twenty-one loops to a degree and a half.

The integrator’s margin, with an ideal output, does not move at all: 90.91 degrees at every capacitance from a picofarad to a hundred nanofarads. The reason is short. Above the input corner the integrator’s feedback factor is a divider of two capacitances, Cf/(Cf+Cs)C_f/(C_f + C_s), and a capacitive divider has no frequency in it. The sensor lowers the loop gain by a constant factor, which moves the crossover down in proportion and adds no phase anywhere. An inverting stage’s feedback factor is a resistance against a capacitance, which is a pole; an integrator’s is a capacitance against a capacitance, which is a number.

That leaves the dashed curve, and it is the finding the tidy argument would have missed. With fifty ohms of output resistance the integrator’s margin does move, dips to 58.3 degrees, and recovers. The output resistance drives the feedback capacitor in series with the sensor, and fifty ohms against CfCs/(Cf+Cs)C_f C_s/(C_f + C_s) is a pole. Its lag at the crossover is small when the sensor is small, because the series capacitance is then small and the pole high; it is small again when the sensor is large, because then the crossover has fallen to GBW Cf/(Cf+Cs)\mathrm{GBW}\,C_f/(C_f + C_s) and the pole, now fixed near 1/(2π⋅50⋅Cf)1/(2\pi \cdot 50 \cdot C_f), is well above it. In between it is worst, and the sweep puts the worst exactly where the sensor equals the feedback capacitor, at ten nanofarads. The closed form — ninety degrees less the arctangent of the measured crossover over that pole — follows every loop to two degrees.

So the integrator’s immunity to its sensor is real and it belongs to the ideal amplifier. A real one’s output resistance brings back a dependence, bounded rather than growing, and a designer who picks a feedback capacitor near the sensor’s own capacitance has picked the worst point on it.

What the amplifier’s own noise sees

The quantity a charge amplifier’s designer cares about most is the gain applied to the amplifier’s own voltage noise, which the gain the loop closes against calls the noise gain and prices for an inverting stage.

With 10 nF at the node the inverting stage's noise gain peaks at 62.1; the integrator's sits at 1 + Cs/Cf = 2.00. computed by solving, not by drawing. The gain from a voltage in series with the amplifier's non-inverting input to the output — the gain its own voltage noise sees — for the inverting stage (solid) and the integrator (dashed), each with 10 nF from the summing junction to ground. The inverting stage's is eleven at low frequency and rises as the capacitance's reactance falls below the resistors, to a peak of 62.08 at 39.8 kHz, where the amplifier runs out. The integrator's is large at low frequency, where the capacitor's reactance dwarfs the input resistor, falls to 1 + Cs/Cf = 2.000 above the input corner 1/(2π·Rin·Cf) = 15.9 kHz, and stays within a fifth of it until the amplifier's bandwidth divided by that number, 500 kHz. Both follow 1 + Zf/Zg to three per cent where the amplifier has gain.
Fig. 3 The gain from a voltage in series with the amplifier’s input to the output, with 10 nF at the summing junction. The inverting stage’s (solid) is eleven at low frequency and peaks at 62.1 at 39.8 kHz. The integrator’s (dashed) falls to 1 + Cs/Cf = 2.00 above its input corner of 15.9 kHz and stays within a fifth of it up to 500 kHz.

Both follow 1+Zf/Zg1 + Z_f/Z_g, the feedback impedance over whatever is between the node and ground, to three per cent wherever the amplifier has gain. For the inverting stage that is 1+Rf/Rin+jωRfCs1 + R_f/R_{in} + j\omega R_f C_s: eleven at low frequency, then rising once the sensor’s reactance falls below the resistors, until the amplifier runs out — which with ten nanofarads happens at a peak of 62.1, at the same 39.8 kHz as the node’s resonance. The amplifier’s voltage noise near that frequency comes out amplified sixty-two times, and it is the reason inverting stages are not used to read capacitive sensors.

For the integrator the same expression is 1+Cs/Cf+1/(jωRinCf)1 + C_s/C_f + 1/(j\omega R_{in} C_f). The last term is large at low frequency, where the input resistor rather than the feedback capacitor decides, and it is gone above 1/(2πRinCf)1/(2\pi R_{in} C_f), 15.9 kHz. What remains is 1+Cs/Cf1 + C_s/C_f, flat at 2.00 with equal capacitances, and it stays within a fifth of that up to 500 kHz, which is the bandwidth divided by the plateau. It never peaks. The integrator’s noise gain is a ratio of capacitances, as its feedback factor was, and the price of a large sensor is a proportionally larger plateau — a flat penalty, set by the ratio of the sensor to the feedback capacitor, with no resonance anywhere to make it worse at one frequency.

The shelf the sensor cannot move

The last reading is the node itself, over the whole band, for four sensors.

The shelf stays at 15.9 Ω whatever the sensor, and the corner above it falls as GBW·Cf/(Cf + Cs). computed by solving, not by drawing. The integrator's summing-junction impedance with 0, 1, 10 and 100 nF of sensor capacitance on the node. In the band the loop gain is the amplifier's gain times Cf/(Cf + Cs) and the open node is the two capacitances in parallel, so their quotient is 1/(2π·GBW·Cf) = 15.92 Ω, with Cs cancelled out of it. What the capacitance moves is where the shelf ends — where that loop gain reaches one, measured at 952 kHz, 850 kHz, 415 kHz, 88.1 kHz against GBW·Cf/(Cf + Cs) = 1.00 MHz, 909 kHz, 500 kHz, 90.9 kHz — and above that the node is the capacitances alone, falling. A charge amplifier's input impedance is set by its feedback capacitor and its amplifier, and not by the sensor it reads.
Fig. 4 The integrator’s summing-junction impedance with 0, 1, 10 and 100 nF on the node. All four sit on the same shelf, 1/(2π·GBW·Cf) = 15.9 Ω. What the sensor moves is where the shelf ends — at the loop’s crossover, measured at 952, 850, 415 and 88.1 kHz against GBW·Cf/(Cf + Cs) = 1.00 MHz, 909, 500 and 90.9 kHz — above which the node falls.

All four curves lie on one shelf. In the band, the node’s open-loop impedance is the two capacitances in parallel, 1/(jω(Cf+Cs))1/(j\omega(C_f + C_s)), and the loop gain is the amplifier’s GBW/(jf)\mathrm{GBW}/(jf) times the divider Cf/(Cf+Cs)C_f/(C_f + C_s). Their quotient is

Znode=12π GBW Cf,Z_{node} = \frac{1}{2\pi\,\mathrm{GBW}\,C_f},

15.9 Ω, with the sensor cancelled out of it. That is the same shelf the earlier essay found as Rin/(1+2π GBW CfRin)R_{in}/(1 + 2\pi\,\mathrm{GBW}\,C_f R_{in}) in the band below the input corner, where the input resistor rather than the sensor is what lies between the node and ground; the two forms agree to 1.6 per cent, the difference being the one in the denominator.

What the sensor does move is the shelf’s upper end. The shelf lasts while the loop gain exceeds one, and the loop gain is divided by 1+Cs/Cf1 + C_s/C_f, so the shelf ends at the crossover, GBW Cf/(Cf+Cs)\mathrm{GBW}\,C_f/(C_f + C_s) in closed form and 952, 850, 415 and 88.1 kHz measured for the four sensors. Above it the node is the capacitances alone and falls. A charge amplifier’s input impedance is set by its feedback capacitor and its amplifier; the sensor decides only how far up the band that holds.

How deep the dip can go

The dip’s depth is worth a formula, since it is the one number the ideal integrator does not warn of. At its worst point the sensor equals the feedback capacitor, the series capacitance is Cf/2C_f/2, and the loop crosses over near half the amplifier’s product. The output pole is at 1/(2πRoutCf/2)1/(2\pi R_{out} C_f/2), so the lag it adds there is about arctan⁡(π GBW Rout Cf/2)\arctan(\pi\,\mathrm{GBW}\,R_{out}\,C_f/2) — a product of the amplifier’s bandwidth, its output resistance and the feedback capacitor, and nothing else. With a megahertz, fifty ohms and ten nanofarads that product gives thirty-eight degrees by the formula; the crossover actually falls a little lower than half the product, to 415 kHz, and the measured loss is 32.6.

The integrator's dip is 4.28° with a 1 nF capacitor and 32.6° with 10 nF on a 1 MHz amplifier, and 69.4° on a 10 MHz one. computed by solving, not by drawing. The phase margin an integrator with 50 Ω of amplifier output resistance loses when a sensor equal to its feedback capacitor sits on its summing junction, against that capacitor from 1 nF to 100 nF, on amplifiers of 1 and 10 MHz (dots), beside arctan(π·GBW·Rout·Cf/2), the lag of the output pole at half the amplifier's bandwidth (lines). At 1 MHz the loss is 4.28° at 1 nF and 32.6° at 10 nF against 38.1° from the expression, which overstates it because the crossover falls below half the bandwidth; at 10 MHz it is 69.4° at 10 nF. The dip scales with the feedback capacitor and with the amplifier's speed together.
Fig. 5 The margin lost with a sensor equal to the feedback capacitor, against that capacitor from 1 nF to 100 nF, on 1 MHz and 10 MHz amplifiers with 50 Ω of output resistance (dots), beside the output pole’s lag at half the amplifier’s bandwidth (lines). At 1 MHz the loss is 4.28° at 1 nF and 32.6° at 10 nF; at 10 MHz it is 69.4° at 10 nF.

Two consequences follow, and the figure above measures both. The dip scales with the feedback capacitor, so a sensitive charge amplifier, with a small CfC_f for a large output per coulomb, barely has one: at one nanofarad the same amplifier loses 4.28°, against 32.6 at ten. And it scales with the amplifier’s bandwidth, so the faster the amplifier the deeper the dip — a 10 MHz amplifier on the same 10 nF loses 69.4° and is left with about twenty degrees, the opposite of the instinct that a faster amplifier is always the more stable choice. The expression overstates every point, and by more as the dip deepens, because the crossover itself falls as the output pole’s lag grows; it is an upper bound to design against rather than a value to quote. Below about 160 pF the comparison stops making sense on this circuit at all: with a 1 kΩ input resistor the loop’s gain never reaches unity, because an integrator’s feedback factor is only as large as 2πfRinCf2\pi f R_{in} C_f below its input corner. The dip is a problem of low-gain charge amplifiers on large sensors with fast amplifiers, and in that corner it is worth the isolating resistor below.

Why the capacitance cancels: the charge picture

The cancellation has a plainer reading than a quotient of two impedances. A capacitive sensor delivers charge. At a summing junction held at ground, that charge has two places to go: into the feedback capacitor, where it becomes an output voltage of −Q/Cf-Q/C_f, or into the sensor’s own capacitance, where it would become a voltage at the node. The loop’s whole job is to keep the node at ground, so the second place is closed off, and the output is −Q/Cf-Q/C_f whatever CsC_s is. That is the charge amplifier’s defining property and the reason long cables do not change its sensitivity.

The loop cannot close it off completely, and how completely is exactly the loop gain. The charge left on the sensor’s capacitance is the fraction (1+Cs/Cf)/(1+T)(1 + C_s/C_f)/(1 + T) of what should have gone to the feedback, which is a gain error, and it is the same 1+Cs/Cf1 + C_s/C_f that sets the noise plateau and divides the loop gain. A sensor ten times the feedback capacitor needs ten times the loop gain for the same accuracy — a statement about precision, not stability, and how much of the amplifier gets through is the measurement of what that loop gain buys at each frequency.

The contrast with the other way of dealing with a cable’s capacitance is instructive. The current that does not reach the input drives a guard at the signal’s own potential, so that a voltage amplifier’s cable carries no current through its capacitance; the source that rings against its guard found that a bootstrapped cable behaves as a capacitance in series with a negative one, and that a source with inductance rings against it. The charge amplifier removes the cable’s voltage rather than its current: the node does not move, so the capacitance has nothing to charge. It is the same capacitance handled from the other end, and the one handled at the virtual earth is the one that cannot ring.

That also marks the limit of the result. Everything above assumes the sensor is only a capacitance. The capacitance that is already a difference met a cable whose two conductors each have their own capacitance to a screen, and a charge amplifier reading one conductor of a pair sees the pair’s capacitance and the screen’s in parallel at its node — both of which cancel here — but a differential charge amplifier reading both conductors sees their mismatch as a common-mode error, which is a different measurement.

What a designer should take

Read a capacitive sensor with an integrator rather than a resistive stage, and the reason is not a matter of degree. The resistive stage’s node is an inductance and the sensor makes it a resonance whose Q grows as the square root of the sensor’s capacitance: its margin falls from ninety degrees towards zero and its noise gain peaks. The integrator’s node is a resistance, its feedback factor a capacitance ratio, and the sensor lowers its loop gain by a constant without adding phase.

Then check the one thing the integrator does see, the amplifier’s output resistance against the two capacitors in series. It costs most when the feedback capacitor equals the sensor; choosing CfC_f well away from CsC_s on either side — smaller for gain, larger for range — keeps it small, and an amplifier with a lower output resistance, or a small resistor isolating the feedback capacitor, removes it.

And expect the noise to scale with the sensor. The integrator’s noise gain is 1+Cs/Cf1 + C_s/C_f over the band, flat, with no peak; a sensor ten times the feedback capacitor multiplies the amplifier’s voltage noise by eleven at every frequency. That is the charge amplifier’s real limitation, and it is a choice of CfC_f rather than a stability problem.

How the numbers were obtained

Each circuit is the same one-pole amplifier model as the earlier essays of this sequence, with its gain of 10510^5, its one-megahertz product and its fifty ohms of output resistance as elements. The node impedance is measured by driving a unit current into the summing junction with every independent source zeroed and reading the voltage, at thirty points a decade. Each margin is found by cutting the loop at the amplifier’s inverting input, driving the amplifier from the cut and reading the voltage returned to the other side, and bisecting the crossover in log frequency; the ideal-output curve is the same loop with the output resistance set to a milliohm. The noise gain is the output voltage for a unit source placed in series with the non-inverting input. The closed forms quoted are checked against the solves and are not used to draw anything.

What it leaves out

The sensor’s own resistance. A piezoelectric sensor has a leakage resistance and a photodiode a shunt resistance in parallel with its capacitance, and a cable a small series resistance. The first is a resistance from the node to ground, which in an integrator adds to the 1/(jωRinCf)1/(j\omega R_{in} C_f) term of the noise gain and makes the low-frequency end worse; the second puts a zero into the capacitive divider at very high frequency.

The amplifier’s second pole. Every loop here has a one-pole amplifier, so the inverting stage’s collapse is entirely the sensor’s pole. A second pole in the amplifier costs both circuits the same lag at a given crossover, and since the integrator’s crossover falls with the sensor, a second pole matters less to it the larger the sensor is.

The feedback resistor every real charge amplifier has. An integrator with nothing across its capacitor has no direct-current feedback and will drift to a rail. A resistor across the capacitor fixes that and changes the node below its own corner, which is the subject of the resistor that holds the bottom of the shelf.

Still open: the feedback resistor, the output isolation, and several sensors on one node

The resistor across the feedback capacitor. Every practical charge amplifier has one, for its direct-current operating point. It turns the bottom of the band into an inverting stage’s node, and where that rising section meets the shelf, and whether it can rise above it, is the next measurement.

A resistor that isolates the output. The fifty-ohm dip is an output resistance against a series capacitance. A few hundred ohms placed deliberately between the amplifier and the feedback capacitor, with the capacitor returned to the amplifier’s output through it, moves that pole and can place it where it costs nothing — or cost more if placed wrongly — and the sensor capacitance at which the choice changes is a line on the same margin axis.

Several sensors on one node. The node that does not care how many put many input resistors on one summing junction and found the ceiling falling with the count. Many capacitive sensors on one integrator’s node sum their capacitances into CsC_s, so the shelf should hold and only its upper end fall; whether the crosstalk between channels follows the same law as for resistors is the question that decides whether a multichannel charge amplifier can share one amplifier.

Part 5 on virtual earth

One argument about Virtual earth, and one of 6 essays on it so far, each part numbered by how much of the idea it assumes. What sits either side of it:

An integrator's summing junction is flat at 15.7 Ω, and worst at direct current. computed by solving, not by drawing. A current is driven into the node and the voltage read. The dashed curve is the same amplifier with a 10 kΩ resistor as its feedback element: a tenth of an ohm at direct current, rising a decade per decade, 909.5 Ω at the top. With a 10 nF capacitor instead, the loop gain has no frequency in it — the amplifier's gain falls as 1/f while the feedback factor rises as f — so it is flat at 62.83 and the node is flat with it, at Rin/(1 + 2π·GBW·C·Rin) = 15.666 Ω, measured 15.668 Ω and holding to 0.50 per cent from 100 Hz to 5.31 kHz — between the amplifier's own pole and the capacitor's corner, which is where a loop gain with no frequency in it lives. Both ends are the other way round from the resistive case: at direct current the capacitor is an open circuit, there is no loop at all, and the node is 843.0 Ω — a factor of 8388 worse than the resistor's 100 mΩ. Above the amplifier's crossover the capacitor is a short and the node is 47.6 Ω against 909.5. The two cross at 1.56 kHz, which is the frequency above which an integrator is the better virtual earth of the two. The shelf a capacitor makes Part 4 — An inverting amplifier's summing node rises a decade per decade to the two resistors in parallel. Replace the feedback resistor with a capacitor and it does neither: an integrator's loop gain has no frequency in it, so the node is flat at Rin/(1 + 2π·GBW·C·Rin) — 15.67 ohms over four decades, to half a per cent. Both ends invert. At direct current the capacitor is an open circuit, there is no loop at all, and the node is 843 ohms against the resistor's tenth of one; above the amplifier's crossover the capacitor is a short and the node is nineteen times better. A 100 kΩ resistor across the capacitor: the node rises a decade per decade and stops at the shelf. computed by solving, not by drawing. The summing-junction impedance of the integrator (1 kΩ in, 10 nF feedback, 1 MHz amplifier) with 100 kΩ across its capacitor (solid), beside the ideal integrator (dashed) and the 10 kΩ inverting stage (dotted). At the lowest frequencies the resistor closes a direct-current loop and the node is 0.999 Ω; it rises a decade per decade, as a resistive stage's does, and stops on the integrator's shelf of 15.9 Ω at the feedback's own corner, 1/(2π·Rp·Cf) = 159 Hz. Its highest point below a tenth of the amplifier's bandwidth is 16.3 Ω. The resistor that holds the bottom of the shelf Part 6 — An integrator's summing junction sits on a flat shelf, 1/(2π·GBW·Cf), over its working band, and at direct current it is nearly its whole input resistor, because a capacitor closes no loop there. A resistor across the capacitor closes one. Below the feedback's own corner the node is then an inverting stage's, rising a decade per decade from Rp/A₀, and the rise meets the shelf exactly at that corner, 1/(2π·Rp·Cf), for any resistor and any amplifier — so the node never rises above its shelf at all. That holds for every resistor below 1/(2π·f₁·Cf), the one that puts the feedback's corner on the amplifier's own pole: 1.59 MΩ here. Above it the bottom climbs past the shelf. The same 1.59 MΩ is where a millivolt of offset becomes 1.58 V at the output, and the price below it is a flat gain of Rp/Rin and arctan(1/(2π·f·Rp·Cf)) of phase.

The objects named here

The third axis, after the field and the idea: the things themselves, and every essay that touches each one.

IntegratorLoadingLoop gainNoise gainPhase marginSumming junction